From: Brijesh Singh <brijesh.singh@amd.com>
To: x86@kernel.org
Cc: bp@alien8.de, Tom Lendacky <thomas.lendacky@amd.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Borislav Petkov <bp@suse.de>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
David Laight <David.Laight@ACULAB.COM>,
Arnd Bergmann <arnd@arndb.de>,
linux-kernel@vger.kernel.org,
Brijesh Singh <brijesh.singh@amd.com>
Subject: [Part1 PATCH v6 13/17] x86/io: Unroll string I/O when SEV is active
Date: Mon, 16 Oct 2017 10:34:19 -0500 [thread overview]
Message-ID: <20171016153423.2980-14-brijesh.singh@amd.com> (raw)
In-Reply-To: <20171016153423.2980-1-brijesh.singh@amd.com>
From: Tom Lendacky <thomas.lendacky@amd.com>
Secure Encrypted Virtualization (SEV) does not support string I/O, so
unroll the string I/O operation into a loop operating on one element at
a time.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Laight <David.Laight@ACULAB.COM>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/io.h | 42 ++++++++++++++++++++++++++++++++++++++----
arch/x86/mm/mem_encrypt.c | 8 ++++++++
2 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index c40a95c33bb8..a785270b53e1 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -265,6 +265,20 @@ static inline void slow_down_io(void)
#endif
+#ifdef CONFIG_AMD_MEM_ENCRYPT
+
+extern struct static_key_false __sev;
+static inline bool sev_key_active(void)
+{
+ return static_branch_unlikely(&__sev);
+}
+
+#else /* !CONFIG_AMD_MEM_ENCRYPT */
+
+static inline bool sev_key_active(void) { return false; }
+
+#endif /* CONFIG_AMD_MEM_ENCRYPT */
+
#define BUILDIO(bwl, bw, type) \
static inline void out##bwl(unsigned type value, int port) \
{ \
@@ -295,14 +309,34 @@ static inline unsigned type in##bwl##_p(int port) \
\
static inline void outs##bwl(int port, const void *addr, unsigned long count) \
{ \
- asm volatile("rep; outs" #bwl \
- : "+S"(addr), "+c"(count) : "d"(port) : "memory"); \
+ if (sev_key_active()) { \
+ unsigned type *value = (unsigned type *)addr; \
+ while (count) { \
+ out##bwl(*value, port); \
+ value++; \
+ count--; \
+ } \
+ } else { \
+ asm volatile("rep; outs" #bwl \
+ : "+S"(addr), "+c"(count) \
+ : "d"(port) : "memory"); \
+ } \
} \
\
static inline void ins##bwl(int port, void *addr, unsigned long count) \
{ \
- asm volatile("rep; ins" #bwl \
- : "+D"(addr), "+c"(count) : "d"(port) : "memory"); \
+ if (sev_key_active()) { \
+ unsigned type *value = (unsigned type *)addr; \
+ while (count) { \
+ *value = in##bwl(port); \
+ value++; \
+ count--; \
+ } \
+ } else { \
+ asm volatile("rep; ins" #bwl \
+ : "+D"(addr), "+c"(count) \
+ : "d"(port) : "memory"); \
+ } \
}
BUILDIO(b, b, char)
diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
index 0c3186755dec..2336c3922227 100644
--- a/arch/x86/mm/mem_encrypt.c
+++ b/arch/x86/mm/mem_encrypt.c
@@ -41,6 +41,8 @@ static char sme_cmdline_off[] __initdata = "off";
*/
u64 sme_me_mask __section(.data) = 0;
EXPORT_SYMBOL_GPL(sme_me_mask);
+DEFINE_STATIC_KEY_FALSE(__sev);
+EXPORT_SYMBOL_GPL(__sev);
static bool sev_enabled __section(.data) = false;
@@ -313,6 +315,12 @@ void __init mem_encrypt_init(void)
if (sev_active())
dma_ops = &sev_dma_ops;
+ /*
+ * With SEV, we need to unroll the rep string I/O instructions.
+ */
+ if (sev_active())
+ static_branch_enable(&__sev);
+
pr_info("AMD %s active\n",
sev_active() ? "Secure Encrypted Virtualization (SEV)"
: "Secure Memory Encryption (SME)");
--
2.9.5
next prev parent reply other threads:[~2017-10-16 15:36 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-16 15:34 [Part1 PATCH v6 00/17] x86: Secure Encrypted Virtualization (AMD) Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 02/17] x86/mm: Add Secure Encrypted Virtualization (SEV) support Brijesh Singh
2017-10-16 16:21 ` Borislav Petkov
2017-10-16 17:46 ` Brijesh Singh
2017-10-16 18:18 ` Borislav Petkov
2017-10-16 19:51 ` [Part1 PATCH v6.1 " Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 03/17] x86/mm: Don't attempt to encrypt initrd under SEV Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 04/17] x86/realmode: Don't decrypt trampoline area " Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 05/17] x86/mm: Use encrypted access of boot related data with SEV Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 06/17] x86/mm: Include SEV for encryption memory attribute changes Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 07/17] x86/efi: Access EFI data as encrypted when SEV is active Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 08/17] resource: Consolidate resource walking code Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 09/17] resource: Provide resource struct in resource walk callback Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 10/17] x86/mm, resource: Use PAGE_KERNEL protection for ioremap of memory pages Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 11/17] x86/mm: Add DMA support for SEV memory encryption Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 12/17] x86/boot: Add early boot support when running with SEV active Brijesh Singh
2017-10-16 15:34 ` Brijesh Singh [this message]
2017-10-16 15:34 ` [Part1 PATCH v6 14/17] x86: Add support for changing memory encryption attribute in early boot Brijesh Singh
2017-10-16 18:20 ` Borislav Petkov
2017-10-16 19:56 ` [Part1 PATCH v6.1 " Brijesh Singh
2017-10-16 21:25 ` Borislav Petkov
2017-10-16 15:34 ` [Part1 PATCH v6 15/17] percpu: Introduce DEFINE_PER_CPU_DECRYPTED Brijesh Singh
2017-10-16 15:34 ` [Part1 PATCH v6 16/17] X86/KVM: Decrypt shared per-cpu variables when SEV is active Brijesh Singh
2017-10-16 22:24 ` Borislav Petkov
2017-10-17 1:43 ` Brijesh Singh
2017-10-17 8:20 ` Borislav Petkov
2017-10-17 11:54 ` Brijesh Singh
2017-10-17 13:35 ` Borislav Petkov
2017-10-17 15:42 ` Brijesh Singh
2017-10-17 16:23 ` Borislav Petkov
2017-10-19 13:44 ` [Part1 PATCH v6.1 " Brijesh Singh
2017-10-19 15:40 ` Borislav Petkov
2017-10-16 15:34 ` [Part1 PATCH v6 17/17] X86/KVM: Clear encryption attribute " Brijesh Singh
2017-10-19 13:47 ` [Part1 PATCH v6.1 " Brijesh Singh
2017-10-16 15:42 ` [Part1 PATCH v6 00/17] x86: Secure Encrypted Virtualization (AMD) Brijesh Singh
2017-10-20 9:24 ` Borislav Petkov
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