Re: [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path

[Leo Yan <leo.yan@arm.com>]

On Mon, Nov 09, 2026 at 04:27:31PM +0000, James Clark wrote:
> 
> 
> On 16/10/2026 17:55, Leo Yan wrote:
> > The Arm ARM (ARM DDI 0487 M.c) rule RDJMDD says:
> > 
> >   | When the following conditions apply, the PE might ignore a direct or
> >   | external write to any of certain Trace Buffer Unit registers, other
> >   | than a direct write or external write to TRBLIMITR_EL1 that clears
> >   | the conditions:
> >   | • TRBLIMITR_EL1.E is 1, and either FEAT_TRBE_EXT is not implemented
> >   |   or the Trace Buffer Unit is using Self-hosted mode.
> > 
> 
> Doesn't the rule just say that the buffer must be disabled before doing
> writes to other registers? But the explanation for removing the extra
> disable is that it's already disabled at this point, so nothing changes.
> 
> The commit message would be clearer without this bit IMO. There's no
> architectural requirement to make this change, it's only a software one.

The rule reference was intended to provide context. The main purpose
is to clarify the rule remains satisfied with this patch.

I will refine the commit log to make it clear.

Thanks,
Leo