* [PATCH v2 01/32] gpu: nova-core: gsp: pass boot context through setup helpers
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 02/32] gpu: nova-core: gsp: decouple boot context from VgpuManager Zhi Wang
` (30 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GSP boot unpacks the device, chipset, BAR and vGPU state from its
context only to pass them to framebuffer setup and GSP_INIT helpers.
The callers duplicate which context fields each helper needs.
Pass GspBootContext through the framebuffer sizing and GSP_INIT payload
helpers. Read the device and mode where they are used, including the
VF topology and WPR2 heap helpers. Keep mode detection, ownership and
firmware values unchanged.
No functional change is intended.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/fb.rs | 26 +++++++++++---------------
drivers/gpu/nova-core/gsp/boot.rs | 2 +-
drivers/gpu/nova-core/gsp/commands.rs | 25 +++++++++----------------
drivers/gpu/nova-core/gsp/hal/gh100.rs | 2 +-
drivers/gpu/nova-core/gsp/hal/tu102.rs | 2 +-
5 files changed, 23 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs
index 5ceb7760c78e..26e94d908b77 100644
--- a/drivers/gpu/nova-core/fb.rs
+++ b/drivers/gpu/nova-core/fb.rs
@@ -174,13 +174,9 @@ pub(crate) struct FbRanges {
impl FbRanges {
/// Computes concrete framebuffer ranges required on non-FSP booting architectures.
- pub(crate) fn new(
- chipset: Chipset,
- bar: Bar0<'_>,
- gsp_fw: &GspFirmware<'_>,
- vgpu_state: VgpuState,
- ) -> Result<Self> {
- let hal = hal::fb_hal(chipset);
+ pub(crate) fn new(ctx: &gsp::GspBootContext<'_, '_>, gsp_fw: &GspFirmware<'_>) -> Result<Self> {
+ let bar = ctx.bar;
+ let hal = hal::fb_hal(ctx.chipset);
let fb = {
let fb_size = hal.vidmem_size(bar);
@@ -242,7 +238,7 @@ pub(crate) fn new(
FbRange(fw_image_addr..fw_image_addr + fw_image_size)
};
- let (vf_partition_count, wpr2_heap_size) = wpr2_heap_params(chipset, vgpu_state, fb.end)?;
+ let (vf_partition_count, wpr2_heap_size) = wpr2_heap_params(ctx, fb.end)?;
let wpr2_heap = {
const WPR2_HEAP_DOWN_ALIGN: Alignment = Alignment::SZ_1M;
@@ -298,11 +294,11 @@ pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option<Range<u64>> {
}
/// Computes the number of VF partitions and the WPR2 heap size from the vGPU state.
-fn wpr2_heap_params(chipset: Chipset, vgpu_state: VgpuState, fb_size: u64) -> Result<(u8, u64)> {
- Ok(match vgpu_state {
+fn wpr2_heap_params(ctx: &gsp::GspBootContext<'_, '_>, fb_size: u64) -> Result<(u8, u64)> {
+ Ok(match ctx.vgpu.state() {
VgpuState::Disabled => (
0,
- gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chipset, fb_size)?,
+ gsp::LibosParams::from_chipset(ctx.chipset).wpr_heap_size(ctx.chipset, fb_size)?,
),
VgpuState::Enabled { total_vfs } => (
u8::try_from(total_vfs.get()).map_err(|_| EINVAL)?,
@@ -328,10 +324,10 @@ pub(crate) struct FbSizes {
impl FbSizes {
/// Computes the framebuffer region sizes for GSP-FMC boot.
- pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, vgpu_state: VgpuState) -> Result<Self> {
- let hal = hal::fb_hal(chipset);
- let fb_size = hal.vidmem_size(bar);
- let (vf_partition_count, wpr2_heap_size) = wpr2_heap_params(chipset, vgpu_state, fb_size)?;
+ pub(crate) fn new(ctx: &gsp::GspBootContext<'_, '_>) -> Result<Self> {
+ let hal = hal::fb_hal(ctx.chipset);
+ let fb_size = hal.vidmem_size(ctx.bar);
+ let (vf_partition_count, wpr2_heap_size) = wpr2_heap_params(ctx, fb_size)?;
Ok(Self {
frts_size: hal.frts_size(),
diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs
index 38ab737ad798..fa879685bac5 100644
--- a/drivers/gpu/nova-core/gsp/boot.rs
+++ b/drivers/gpu/nova-core/gsp/boot.rs
@@ -123,7 +123,7 @@ pub(crate) fn boot(
// GSP-RM discards any RPC that reaches it before GSP_INIT, so the system information
// and the registry keys go inside that one request.
- let init_payload = commands::build_gsp_init_payload(pdev, chipset, ctx.vgpu.state())?;
+ let init_payload = commands::build_gsp_init_payload(ctx)?;
let bootloader = if super::hal::uses_generic_bootloader(chipset) {
Some(GenericBootloader::new(dev, chipset, gsp_falcon)?)
} else {
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 6d250548c165..ce1761c2f398 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -8,14 +8,12 @@
};
use kernel::{
- device,
pci,
prelude::*,
transmute::AsBytes, //
};
use crate::{
- gpu::Chipset,
gsp::{
cmdq::{
Cmdq,
@@ -40,6 +38,7 @@
Encoder,
UnknownKeyPolicy, //
},
+ GspBootContext,
},
sbuffer::SBufferIter,
vgpu::VgpuState, //
@@ -103,37 +102,31 @@ pub(crate) fn gpu_name(&self) -> core::result::Result<&str, GpuNameError> {
/// - `ENODEV` if vGPU mode is enabled but the SR-IOV capability is missing.
///
/// Errors reading the PCI configuration or decoding the VF BAR layout are propagated as-is.
-pub(crate) fn build_gsp_init_payload(
- pdev: &pci::Device<device::Bound>,
- chipset: Chipset,
- vgpu_state: VgpuState,
-) -> Result<EncodedStream> {
+pub(super) fn build_gsp_init_payload(ctx: &GspBootContext<'_, '_>) -> Result<EncodedStream> {
let mut regkeys = KVVec::new();
for &(name, value) in REGISTRY_ENTRIES {
regkeys.push(RegKey::new(name, value), GFP_KERNEL)?;
}
- if matches!(vgpu_state, VgpuState::Enabled { .. }) {
+ if matches!(ctx.vgpu.state(), VgpuState::Enabled { .. }) {
regkeys.push(RegKey::new(b"RMSetSriovMode\0", 1), GFP_KERNEL)?;
}
- let vf_info = build_vf_info(pdev, vgpu_state)?;
+ let vf_info = build_vf_info(ctx)?;
let mut encoder = Encoder::new();
- GspInitRequest::new(pdev, chipset, regkeys, vf_info).encode(&mut encoder)?;
+ GspInitRequest::new(ctx.pdev, ctx.chipset, regkeys, vf_info).encode(&mut encoder)?;
Ok(encoder.finish())
}
/// Builds the optional VF topology portion of the `GSP_INIT` request.
-fn build_vf_info(
- pdev: &pci::Device<device::Bound>,
- vgpu_state: VgpuState,
-) -> Result<Option<VfInfo>> {
- let VgpuState::Enabled { total_vfs } = vgpu_state else {
+fn build_vf_info(ctx: &GspBootContext<'_, '_>) -> Result<Option<VfInfo>> {
+ let VgpuState::Enabled { total_vfs } = ctx.vgpu.state() else {
return Ok(None);
};
- let sriov = pdev
+ let sriov = ctx
+ .pdev
.config_space_extended()?
.find_ext_capability::<pci::ExtSriovRegs>()?
.ok_or(ENODEV)?;
diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core/gsp/hal/gh100.rs
index 91201b51030e..f91cdd061706 100644
--- a/drivers/gpu/nova-core/gsp/hal/gh100.rs
+++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs
@@ -151,7 +151,7 @@ fn boot<'gpu>(
let chipset = ctx.chipset;
let gsp_falcon = ctx.gsp_falcon;
- let fb_sizes = FbSizes::new(chipset, ctx.bar, ctx.vgpu.state())?;
+ let fb_sizes = FbSizes::new(ctx)?;
dev_dbg!(dev, "{:#x?}\n", fb_sizes);
let wpr_meta =
diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs
index bbdcf754ec13..c3a87e5c7e0b 100644
--- a/drivers/gpu/nova-core/gsp/hal/tu102.rs
+++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs
@@ -259,7 +259,7 @@ fn boot<'gpu>(
let gsp_falcon = ctx.gsp_falcon;
let sec2_falcon = ctx.sec2_falcon;
- let fb_ranges = FbRanges::new(chipset, bar, gsp_fw, ctx.vgpu.state())?;
+ let fb_ranges = FbRanges::new(ctx, gsp_fw)?;
dev_dbg!(dev, "{:#x?}\n", fb_ranges);
// Declared before the unload guard so that if Booter fails while running, SEC2 is reset
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 02/32] gpu: nova-core: gsp: decouple boot context from VgpuManager
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
2026-09-14 7:48 ` [PATCH v2 01/32] gpu: nova-core: gsp: pass boot context through setup helpers Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 03/32] gpu: nova-core: vgpu: detect boot state independently Zhi Wang
` (29 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GSP boot uses the detected vGPU mode to size firmware resources and
populate GSP_INIT. Carrying the whole manager in the boot and unload
context couples these operations to its runtime interface.
The boot code only needs read access to the mode, and unloading does
not use the manager. A short state borrow is sufficient for both
context construction sites.
Make GspBootContext borrow VgpuState directly and read it in the
framebuffer and GSP_INIT helpers. Return a state reference from the
manager without changing mode detection or the values passed to firmware.
No functional change is intended.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/fb.rs | 2 +-
drivers/gpu/nova-core/gpu.rs | 4 ++--
drivers/gpu/nova-core/gsp.rs | 4 ++--
drivers/gpu/nova-core/gsp/commands.rs | 4 ++--
drivers/gpu/nova-core/vgpu.rs | 4 ++--
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs
index 26e94d908b77..882827bcfd3a 100644
--- a/drivers/gpu/nova-core/fb.rs
+++ b/drivers/gpu/nova-core/fb.rs
@@ -295,7 +295,7 @@ pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option<Range<u64>> {
/// Computes the number of VF partitions and the WPR2 heap size from the vGPU state.
fn wpr2_heap_params(ctx: &gsp::GspBootContext<'_, '_>, fb_size: u64) -> Result<(u8, u64)> {
- Ok(match ctx.vgpu.state() {
+ Ok(match *ctx.vgpu_state {
VgpuState::Disabled => (
0,
gsp::LibosParams::from_chipset(ctx.chipset).wpr_heap_size(ctx.chipset, fb_size)?,
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 4b562a8687b6..cf24c0d00173 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -359,7 +359,7 @@ fn drop(self: Pin<&mut Self>) {
gsp_falcon: &*this.gsp_falcon,
sec2_falcon: &*this.sec2_falcon,
fsp: this.fsp.as_mut(),
- vgpu: &*this.vgpu,
+ vgpu_state: this.vgpu.state(),
},
bundle,
)
@@ -424,7 +424,7 @@ pub(crate) fn new<'a>(
gsp_falcon,
sec2_falcon,
fsp: fsp.as_mut(),
- vgpu,
+ vgpu_state: vgpu.state(),
})?,
}),
diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs
index d043954fe4a7..93291c67d6de 100644
--- a/drivers/gpu/nova-core/gsp.rs
+++ b/drivers/gpu/nova-core/gsp.rs
@@ -49,7 +49,7 @@
fw::GspArgumentsPadded, //
},
num,
- vgpu::VgpuManager, //
+ vgpu::VgpuState, //
};
pub(crate) const GSP_PAGE_SHIFT: usize = 12;
@@ -68,7 +68,7 @@ pub(crate) struct GspBootContext<'ctx, 'gpu> {
pub(crate) gsp_falcon: &'ctx Falcon<'gpu, GspFalcon>,
pub(crate) sec2_falcon: &'ctx Falcon<'gpu, Sec2Falcon>,
pub(crate) fsp: Option<&'ctx mut Fsp<'gpu>>,
- pub(crate) vgpu: &'ctx VgpuManager,
+ pub(crate) vgpu_state: &'ctx VgpuState,
}
impl<'ctx, 'gpu> GspBootContext<'ctx, 'gpu> {
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index ce1761c2f398..09223bc3b793 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -107,7 +107,7 @@ pub(super) fn build_gsp_init_payload(ctx: &GspBootContext<'_, '_>) -> Result<Enc
for &(name, value) in REGISTRY_ENTRIES {
regkeys.push(RegKey::new(name, value), GFP_KERNEL)?;
}
- if matches!(ctx.vgpu.state(), VgpuState::Enabled { .. }) {
+ if matches!(*ctx.vgpu_state, VgpuState::Enabled { .. }) {
regkeys.push(RegKey::new(b"RMSetSriovMode\0", 1), GFP_KERNEL)?;
}
@@ -121,7 +121,7 @@ pub(super) fn build_gsp_init_payload(ctx: &GspBootContext<'_, '_>) -> Result<Enc
/// Builds the optional VF topology portion of the `GSP_INIT` request.
fn build_vf_info(ctx: &GspBootContext<'_, '_>) -> Result<Option<VfInfo>> {
- let VgpuState::Enabled { total_vfs } = ctx.vgpu.state() else {
+ let VgpuState::Enabled { total_vfs } = *ctx.vgpu_state else {
return Ok(None);
};
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 6b7e045acea8..905b3a7331fd 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -85,7 +85,7 @@ fn detect_state(
}
/// Returns the detected vGPU state for this boot.
- pub(crate) fn state(&self) -> VgpuState {
- self.state
+ pub(crate) fn state(&self) -> &VgpuState {
+ &self.state
}
}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 03/32] gpu: nova-core: vgpu: detect boot state independently
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
2026-09-14 7:48 ` [PATCH v2 01/32] gpu: nova-core: gsp: pass boot context through setup helpers Zhi Wang
2026-09-14 7:48 ` [PATCH v2 02/32] gpu: nova-core: gsp: decouple boot context from VgpuManager Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 04/32] gpu: nova-core: gpu: add a channel ID pool for vGPU Zhi Wang
` (28 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The vGPU manager currently contains only the detected boot mode. Its
construction couples mode detection to an object with no runtime
management responsibilities.
Firmware setup needs the mode before allocating GSP resources, even
when vGPU is disabled. Keeping that value with GspResources also makes
it available throughout the firmware lifecycle without a manager.
Move detection to VgpuState and store its result in GspResources.
Borrow it directly when constructing the boot and unload contexts, and
remove the state-only manager wrapper. Preserve the FSP query order,
existing diagnostics and disabled fallback.
No functional change is intended.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 11 +++++------
drivers/gpu/nova-core/vgpu.rs | 25 ++++++++-----------------
2 files changed, 13 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index cf24c0d00173..39e9e4ab0be6 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -48,7 +48,7 @@
GpuMm,
VramAddress, //
},
- vgpu::VgpuManager, //
+ vgpu::VgpuState, //
};
#[cfg_attr(not(CONFIG_KUNIT = "y"), expect(dead_code))]
@@ -294,8 +294,7 @@ struct GspResources<'gpu> {
// TODO: use different resource types for each boot method, and make the relevant Gsp methods
// generic against them.
fsp: Option<Fsp<'gpu>>,
- /// vGPU state detected before GSP boot.
- vgpu: VgpuManager,
+ vgpu_state: VgpuState,
/// GSP runtime data.
#[pin]
gsp: Gsp<'gpu>,
@@ -359,7 +358,7 @@ fn drop(self: Pin<&mut Self>) {
gsp_falcon: &*this.gsp_falcon,
sec2_falcon: &*this.sec2_falcon,
fsp: this.fsp.as_mut(),
- vgpu_state: this.vgpu.state(),
+ vgpu_state: this.vgpu_state,
},
bundle,
)
@@ -410,7 +409,7 @@ pub(crate) fn new<'a>(
fsp: Fsp::try_new(dev, bar, spec.chipset)?,
- vgpu: VgpuManager::new(pdev, spec.chipset, fsp.as_mut()),
+ vgpu_state: VgpuState::detect(pdev, spec.chipset, fsp.as_mut()),
gsp <- Gsp::new(pdev, bar),
@@ -424,7 +423,7 @@ pub(crate) fn new<'a>(
gsp_falcon,
sec2_falcon,
fsp: fsp.as_mut(),
- vgpu_state: vgpu.state(),
+ vgpu_state,
})?,
}),
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 905b3a7331fd..b405ba49c490 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -30,19 +30,16 @@ pub(crate) enum VgpuState {
},
}
-/// vGPU state manager.
-pub(crate) struct VgpuManager {
- state: VgpuState,
-}
-
-impl VgpuManager {
- /// Creates a vGPU manager by querying SR-IOV and the FSP PRC vGPU knob.
- pub(crate) fn new(
+impl VgpuState {
+ /// Detects the boot mode, falling back to disabled if querying the device fails.
+ ///
+ /// Call after creating the FSP and before allocating GSP firmware resources.
+ pub(crate) fn detect(
pdev: &pci::Device<device::Core<'_>>,
chipset: Chipset,
fsp: Option<&mut Fsp<'_>>,
) -> Self {
- let state = Self::detect_state(pdev, chipset, fsp).unwrap_or_else(|e| {
+ let state = Self::query_state(pdev, chipset, fsp).unwrap_or_else(|e| {
dev_warn!(
pdev,
"vGPU state detection failed: {:?}; disabling vGPU\n",
@@ -51,12 +48,11 @@ pub(crate) fn new(
VgpuState::Disabled
});
dev_dbg!(pdev, "vGPU state: {:?}\n", state);
-
- Self { state }
+ state
}
/// Detects the vGPU state from the chipset, SR-IOV capability and FSP PRC knob.
- fn detect_state(
+ fn query_state(
pdev: &pci::Device<device::Core<'_>>,
chipset: Chipset,
fsp: Option<&mut Fsp<'_>>,
@@ -83,9 +79,4 @@ fn detect_state(
VgpuMode::Disabled => Ok(VgpuState::Disabled),
}
}
-
- /// Returns the detected vGPU state for this boot.
- pub(crate) fn state(&self) -> &VgpuState {
- &self.state
- }
}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 04/32] gpu: nova-core: gpu: add a channel ID pool for vGPU
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (2 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 03/32] gpu: nova-core: vgpu: detect boot state independently Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 05/32] gpu: nova-core: gsp: expose the VMMU segment size Zhi Wang
` (27 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
Channel ID reservations need a GPU-owned pool shared by vGPU instances.
The existing allocator is not instantiated by Gpu, leaving no common
pool from which consumers can reserve per-VF ranges.
The pool must remain at a stable address while its reservations exist.
Its storage also needs to remain available throughout GPU cleanup.
Create a private pinned ChannelIdPool with a single 2048-channel
capacity constant. Initialize it before GSP resources and declare it
after them so that it survives both their normal destruction and
initialization rollback. No channel reservations are made here.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 9 +++++++++
drivers/gpu/nova-core/gpu/channel.rs | 4 ++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 39e9e4ab0be6..733a2c09ec01 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -48,6 +48,7 @@
GpuMm,
VramAddress, //
},
+ num,
vgpu::VgpuState, //
};
@@ -56,6 +57,10 @@
mod hal;
mod regs;
+use self::channel::TOTAL_CHANNELS;
+
+pub(crate) use self::channel::ChannelIdPool;
+
macro_rules! define_chipset {
({ $($variant:ident = $value:expr),* $(,)* }) =>
{
@@ -322,6 +327,8 @@ pub(crate) struct Gpu<'gpu> {
/// GSP and its resources.
#[pin]
gsp_resources: GspResources<'gpu>,
+ #[pin]
+ chid_pool: ChannelIdPool,
/// System memory page required for flushing all pending GPU-side memory writes done through
/// PCIE into system memory, via sysmembar (A GPU-initiated HW memory-barrier operation).
///
@@ -396,6 +403,8 @@ pub(crate) fn new<'a>(
// Initialize this early because `gsp_resources` depends on it.
sysmem_flush: SysmemFlush::register(dev, bar, spec.chipset)?,
+ chid_pool <- ChannelIdPool::new(cv!(num::u32_as_usize(TOTAL_CHANNELS))),
+
gsp_resources <- try_pin_init!(GspResources {
device: pdev,
diff --git a/drivers/gpu/nova-core/gpu/channel.rs b/drivers/gpu/nova-core/gpu/channel.rs
index 485efaba059d..75666c6768e6 100644
--- a/drivers/gpu/nova-core/gpu/channel.rs
+++ b/drivers/gpu/nova-core/gpu/channel.rs
@@ -21,6 +21,10 @@
}, //
};
+// TODO: Query the channel capacity through GMCAPI once an equivalent of
+// NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS is available.
+pub(super) const TOTAL_CHANNELS: u32 = 2048;
+
/// Pool for tracking reservations of channel IDs.
#[pin_data]
pub(crate) struct ChannelIdPool {
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 05/32] gpu: nova-core: gsp: expose the VMMU segment size
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (3 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 04/32] gpu: nova-core: gpu: add a channel ID pool for vGPU Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 06/32] gpu: nova-core: gsp: decode the FIFO engine table Zhi Wang
` (26 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GSP_INIT reports the VMMU segment size needed to align vGPU guest memory
allocations.
Add a getter for the existing decoded value and propagate it into
GetGspStaticInfoReply. Keep zero when firmware omits the optional key.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/commands.rs | 4 ++++
drivers/gpu/nova-core/gsp/fw/commands.rs | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 09223bc3b793..afc32c2a230e 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -53,6 +53,9 @@ pub(crate) struct GetGspStaticInfoReply {
pub(crate) usable_fb_regions: KVec<Range<u64>>,
/// Exclusive end of the FB physical address space.
pub(crate) total_fb_end: u64,
+ /// VMMU segment size in bytes, or zero if GSP-RM omitted it.
+ #[expect(dead_code)]
+ pub(crate) vmmu_segment_size: u64,
}
/// Error type for [`GetGspStaticInfoReply::gpu_name`].
@@ -276,6 +279,7 @@ fn decode_gsp_info(words: &[u64]) -> Result<GetGspStaticInfoReply> {
bar1_pde_base: decoded.bar1_pde_base(),
usable_fb_regions,
total_fb_end: decoded.total_fb_end().ok_or(EINVAL)?,
+ vmmu_segment_size: decoded.vmmu_segment_size(),
})
}
diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-core/gsp/fw/commands.rs
index 2b9f8edb039d..c2e199688b79 100644
--- a/drivers/gpu/nova-core/gsp/fw/commands.rs
+++ b/drivers/gpu/nova-core/gsp/fw/commands.rs
@@ -367,6 +367,11 @@ pub(crate) fn total_fb_end(&self) -> Option<u64> {
.max()?
.checked_add(1)
}
+
+ /// Returns the VMMU segment size in bytes, or zero if GSP-RM omitted it.
+ pub(in crate::gsp) const fn vmmu_segment_size(&self) -> u64 {
+ self.vmmu_segment_size
+ }
}
nvkv_decode! {
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 06/32] gpu: nova-core: gsp: decode the FIFO engine table
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (4 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 05/32] gpu: nova-core: gsp: expose the VMMU segment size Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 07/32] gpu: nova-core: vgpu: initialize runtime parameters after GSP boot Zhi Wang
` (25 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
From: Alok Kumar <alkumar@nvidia.com>
GSP_INIT reports the FIFO engine table needed to build the engine bitmap
used during vGPU instance creation.
Decode the engine count, GMC IDs and flags, and expose host-driven
engines in GetGspStaticInfoReply. Preserve firmware FIFO order and
duplicate IDs while filtering on the host-driven flag.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Co-developed-by: Zhi Wang <zhiw@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/commands.rs | 47 +++++++++++++++++++++++-
drivers/gpu/nova-core/gsp/fw/commands.rs | 34 ++++++++++++++++-
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index afc32c2a230e..3820320dcb34 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -26,7 +26,8 @@
GspInitResponse,
GspInitResponseSchema,
RegKey,
- VfInfo, //
+ VfInfo,
+ MAX_FIFO_ENGINES, //
},
GMCAPI_CMD_GSP_INIT,
GMCAPI_CMD_GSP_SUSPEND, //
@@ -44,6 +45,28 @@
vgpu::VgpuState, //
};
+/// Bit mask for `NVGMC_SC_ENGINE_FLAGS_IS_HOST_DRIVEN`.
+const ENGINE_FLAGS_IS_HOST_DRIVEN: u32 = 1 << 0;
+
+/// Host-driven GMC engine IDs in hardware FIFO order, including any repeated IDs.
+///
+/// # Invariants
+///
+/// `count` is at most [`MAX_FIFO_ENGINES`]. The first `count` slots are the retained engine IDs.
+#[derive(Copy, Clone)]
+pub(crate) struct FifoEngineList {
+ gmc_ids: [u32; MAX_FIFO_ENGINES],
+ count: usize,
+}
+
+impl FifoEngineList {
+ #[expect(dead_code)]
+ pub(crate) fn gmc_ids(&self) -> &[u32] {
+ // PANIC: The type invariant bounds `count` by the array capacity.
+ &self.gmc_ids[..self.count]
+ }
+}
+
/// The static GPU configuration, as decoded from the `GSP_INIT` reply.
pub(crate) struct GetGspStaticInfoReply {
gpu_name: [u8; 64],
@@ -56,6 +79,8 @@ pub(crate) struct GetGspStaticInfoReply {
/// VMMU segment size in bytes, or zero if GSP-RM omitted it.
#[expect(dead_code)]
pub(crate) vmmu_segment_size: u64,
+ #[expect(dead_code)]
+ pub(crate) fifo_engine_list: FifoEngineList,
}
/// Error type for [`GetGspStaticInfoReply::gpu_name`].
@@ -274,12 +299,32 @@ fn decode_gsp_info(words: &[u64]) -> Result<GetGspStaticInfoReply> {
usable_fb_regions.push(region, GFP_KERNEL)?;
}
+ // INVARIANT: The list starts empty and appends at most one ID per supported input slot.
+ let mut fifo_engine_list = FifoEngineList {
+ gmc_ids: [0; MAX_FIFO_ENGINES],
+ count: 0,
+ };
+ for (&gmc_id, &flags) in decoded
+ .fifo_engine_gmc_ids()
+ .iter()
+ .zip(decoded.fifo_engine_flags())
+ .take(decoded.fifo_engine_count())
+ {
+ if flags & ENGINE_FLAGS_IS_HOST_DRIVEN != 0 {
+ // PANIC: At most one slot is filled per input, and the input has at most
+ // MAX_FIFO_ENGINES entries, so the next retained ID always fits.
+ fifo_engine_list.gmc_ids[fifo_engine_list.count] = gmc_id;
+ fifo_engine_list.count += 1;
+ }
+ }
+
Ok(GetGspStaticInfoReply {
gpu_name,
bar1_pde_base: decoded.bar1_pde_base(),
usable_fb_regions,
total_fb_end: decoded.total_fb_end().ok_or(EINVAL)?,
vmmu_segment_size: decoded.vmmu_segment_size(),
+ fifo_engine_list,
})
}
diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-core/gsp/fw/commands.rs
index c2e199688b79..706ecfa63c01 100644
--- a/drivers/gpu/nova-core/gsp/fw/commands.rs
+++ b/drivers/gpu/nova-core/gsp/fw/commands.rs
@@ -12,7 +12,10 @@
transmute::AsBytes, //
};
-use crate::gpu::Chipset;
+use crate::{
+ gpu::Chipset,
+ num, //
+};
use crate::gsp::nvkv::{
nvkv_decode,
@@ -22,6 +25,7 @@
DecoderValue,
Encodable,
Encoder,
+ Indexed,
Key,
KeyId,
Required, //
@@ -286,6 +290,8 @@ pub(crate) fn new(
// Decode:
+pub(in crate::gsp) const MAX_FIFO_ENGINES: usize = 64;
+
// Should decode with UnknownKeyPolicy::Ignore.
nvkv_decode! {
/// Schema for the `GSP_INIT` response.
@@ -298,6 +304,9 @@ pub(crate) struct GspInitResponseSchema => GspInitResponse {
fb_regions: Accumulated<FbRegionSchema>,
bar1_pde_base: Required<u64, { Self::BAR1_PDE_BASE_KEY }>,
vmmu_segment_size: Key<u64, { Self::VMMU_SEGMENT_SIZE_KEY }>,
+ fifo_engine_count: Key<u32, { Self::FIFO_ENGINE_COUNT_KEY }>,
+ fifo_engine_gmc_ids: Indexed<u32, MAX_FIFO_ENGINES, { Self::FIFO_ENGINE_GMC_ID_KEY }>,
+ fifo_engine_flags: Indexed<u32, MAX_FIFO_ENGINES, { Self::FIFO_ENGINE_FLAGS_KEY }>,
}
}
@@ -306,6 +315,9 @@ impl GspInitResponseSchema {
const GPU_NAME_STRING_KEY: KeyId = 0x2000;
const BAR1_PDE_BASE_KEY: KeyId = 0x1020;
const VMMU_SEGMENT_SIZE_KEY: KeyId = 0x1050;
+ const FIFO_ENGINE_COUNT_KEY: KeyId = 0x0500;
+ const FIFO_ENGINE_GMC_ID_KEY: KeyId = 0x0501;
+ const FIFO_ENGINE_FLAGS_KEY: KeyId = 0x0502;
}
/// Payload of the `GSP_INIT` response.
@@ -315,6 +327,9 @@ pub(crate) struct GspInitResponse {
fb_regions: KVVec<FbRegion>,
bar1_pde_base: u64,
vmmu_segment_size: u64,
+ fifo_engine_count: u32,
+ fifo_engine_gmc_ids: [u32; MAX_FIFO_ENGINES],
+ fifo_engine_flags: [u32; MAX_FIFO_ENGINES],
}
impl GspInitResponse {
@@ -372,6 +387,23 @@ pub(crate) fn total_fb_end(&self) -> Option<u64> {
pub(in crate::gsp) const fn vmmu_segment_size(&self) -> u64 {
self.vmmu_segment_size
}
+
+ /// Returns the FIFO engine count, limited to the supported table capacity.
+ ///
+ /// An omitted count is zero. Indexed entries outside the capacity are rejected during decode.
+ pub(in crate::gsp) fn fifo_engine_count(&self) -> usize {
+ num::u32_as_usize(self.fifo_engine_count).min(MAX_FIFO_ENGINES)
+ }
+
+ /// Returns GMC engine IDs by hardware FIFO order; omitted slots contain zero.
+ pub(in crate::gsp) fn fifo_engine_gmc_ids(&self) -> &[u32; MAX_FIFO_ENGINES] {
+ &self.fifo_engine_gmc_ids
+ }
+
+ /// Returns per-engine flags by hardware FIFO order; omitted slots contain zero.
+ pub(in crate::gsp) fn fifo_engine_flags(&self) -> &[u32; MAX_FIFO_ENGINES] {
+ &self.fifo_engine_flags
+ }
}
nvkv_decode! {
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 07/32] gpu: nova-core: vgpu: initialize runtime parameters after GSP boot
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (5 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 06/32] gpu: nova-core: gsp: decode the FIFO engine table Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 08/32] gpu: nova-core: vgpu: reserve the 48-VM WPR2 heap Zhi Wang
` (24 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GSP_INIT reports the VMMU segment size and FIFO engine topology needed
to divide resources among vGPU instances.
These resources are only meaningful after a successful vGPU-enabled
boot. A disabled GPU should not construct a manager, and a constructed
manager should always have its complete runtime parameters.
Have Gpu construct an optional VgpuManager from BootResult::static_info
after GSP boot. Copy the ordered engine list and VMMU segment size, use
the pool's 2048-channel capacity, and store them directly in the manager.
Expose read-only accessors tied to the manager, preserving a reported
VMMU size of zero.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 23 ++++++++++++-
drivers/gpu/nova-core/gsp/commands.rs | 2 --
drivers/gpu/nova-core/vgpu.rs | 48 ++++++++++++++++++++++++++-
3 files changed, 69 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 733a2c09ec01..227531b28541 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -49,7 +49,10 @@
VramAddress, //
},
num,
- vgpu::VgpuState, //
+ vgpu::{
+ VgpuManager,
+ VgpuState, //
+ },
};
#[cfg_attr(not(CONFIG_KUNIT = "y"), expect(dead_code))]
@@ -311,6 +314,7 @@ struct GspResources<'gpu> {
#[pin_data]
pub(crate) struct Gpu<'gpu> {
spec: Spec,
+ vgpu: Option<VgpuManager<'gpu>>,
/// GSP event interrupt registration.
///
/// Declared before `gsp_resources` so it is dropped first: `free_irq` runs, waiting out any
@@ -436,6 +440,23 @@ pub(crate) fn new<'a>(
})?,
}),
+ vgpu: {
+ let info = &gsp_resources.boot_result.static_info;
+ match gsp_resources.vgpu_state {
+ VgpuState::Disabled => None,
+ VgpuState::Enabled { .. } => Some(VgpuManager::new(
+ // SAFETY: `chid_pool` is initialized above at its final pinned address.
+ // The private manager and its pool borrow cannot escape this `Gpu`.
+ // Completed field drop order drops the manager before the pool; on failure,
+ // pin-init drops it before the earlier-initialized pool.
+ unsafe { &*core::ptr::from_ref(chid_pool.as_ref().get_ref()) },
+ &info.fifo_engine_list,
+ info.vmmu_segment_size,
+ TOTAL_CHANNELS,
+ )),
+ }
+ },
+
// GSP boot left the SWGEN0 latch set and pending bits in the tree.
_: {
irq::gsp::quiesce(bar, gsp_resources.spec.chipset, vectors_ref)?;
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 3820320dcb34..c2faa825a849 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -77,9 +77,7 @@ pub(crate) struct GetGspStaticInfoReply {
/// Exclusive end of the FB physical address space.
pub(crate) total_fb_end: u64,
/// VMMU segment size in bytes, or zero if GSP-RM omitted it.
- #[expect(dead_code)]
pub(crate) vmmu_segment_size: u64,
- #[expect(dead_code)]
pub(crate) fifo_engine_list: FifoEngineList,
}
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index b405ba49c490..348af9ea3fc2 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -13,7 +13,11 @@
Fsp,
VgpuMode, //
},
- gpu::Chipset, //
+ gpu::{
+ ChannelIdPool,
+ Chipset, //
+ },
+ gsp::commands::FifoEngineList, //
};
mod hal;
@@ -80,3 +84,45 @@ fn query_state(
}
}
}
+
+/// Runtime resources for an enabled vGPU boot.
+pub(crate) struct VgpuManager<'gpu> {
+ #[expect(dead_code)]
+ chid_pool: &'gpu ChannelIdPool,
+ vmmu_segment_size: u64,
+ total_channels: u32,
+ fifo_engine_list: FifoEngineList,
+}
+
+impl<'gpu> VgpuManager<'gpu> {
+ /// Retains runtime parameters from a completed vGPU-enabled GSP boot.
+ pub(crate) fn new(
+ chid_pool: &'gpu ChannelIdPool,
+ fifo_engine_list: &FifoEngineList,
+ vmmu_segment_size: u64,
+ total_channels: u32,
+ ) -> Self {
+ Self {
+ chid_pool,
+ vmmu_segment_size,
+ total_channels,
+ fifo_engine_list: *fifo_engine_list,
+ }
+ }
+
+ /// Returns the VMMU segment size in bytes, or zero if GSP-RM omitted it.
+ #[expect(dead_code)]
+ const fn vmmu_segment_size(&self) -> u64 {
+ self.vmmu_segment_size
+ }
+
+ #[expect(dead_code)]
+ const fn total_channels(&self) -> u32 {
+ self.total_channels
+ }
+
+ #[expect(dead_code)]
+ fn fifo_engine_list(&self) -> &FifoEngineList {
+ &self.fifo_engine_list
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 08/32] gpu: nova-core: vgpu: reserve the 48-VM WPR2 heap
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (6 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 07/32] gpu: nova-core: vgpu: initialize runtime parameters after GSP boot Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 09/32] gpu: nova-core: mm: borrow BarUser for temporary BAR1 access Zhi Wang
` (23 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GSP-RM needs the larger r000 vGPU WPR2 heap on devices that
advertise more than 32 VFs. The default heap is too small for the 48-VF
GB202 configuration and GSP-RM fails to start.
Select the firmware-defined 48-VM size from the detected VF count while
retaining the default size for configurations with 2 through 32 VFs.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/fb.rs | 2 +-
drivers/gpu/nova-core/gsp/fw.rs | 7 +++++--
drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs | 1 +
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs
index 882827bcfd3a..ba68a812b095 100644
--- a/drivers/gpu/nova-core/fb.rs
+++ b/drivers/gpu/nova-core/fb.rs
@@ -302,7 +302,7 @@ fn wpr2_heap_params(ctx: &gsp::GspBootContext<'_, '_>, fb_size: u64) -> Result<(
),
VgpuState::Enabled { total_vfs } => (
u8::try_from(total_vfs.get()).map_err(|_| EINVAL)?,
- gsp::LibosParams::vgpu_wpr_heap_size(),
+ gsp::LibosParams::vgpu_wpr_heap_size(total_vfs.get()),
),
})
}
diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs
index 77a66f77f4b2..309f9296ebc8 100644
--- a/drivers/gpu/nova-core/gsp/fw.rs
+++ b/drivers/gpu/nova-core/gsp/fw.rs
@@ -129,8 +129,11 @@ pub(crate) fn from_chipset(chipset: Chipset) -> &'static LibosParams {
}
/// Returns the WPR heap size to reserve when vGPU is enabled.
- pub(crate) fn vgpu_wpr_heap_size() -> u64 {
- u64::from(bindings::GSP_FW_HEAP_SIZE_VGPU_DEFAULT)
+ pub(crate) fn vgpu_wpr_heap_size(total_vfs: u16) -> u64 {
+ u64::from(match total_vfs {
+ 2..=32 => bindings::GSP_FW_HEAP_SIZE_VGPU_DEFAULT,
+ _ => r000_00::GSP_FW_HEAP_SIZE_VGPU_48VMS,
+ })
}
/// Returns the amount of memory (in bytes) to allocate for the WPR heap for a framebuffer size
diff --git a/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs b/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
index 454d0ea9360f..fa17d3e2edf6 100644
--- a/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
+++ b/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
@@ -84,6 +84,7 @@ impl<T> ::core::cmp::Eq for __BindgenUnionField<T> {}
pub const GSP_FW_HEAP_PARAM_SIZE_PER_GB: u32 = 98304;
pub const GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE: u32 = 100663296;
pub const GSP_FW_HEAP_SIZE_VGPU_DEFAULT: u32 = 609222656;
+pub const GSP_FW_HEAP_SIZE_VGPU_48VMS: u32 = 1436549120;
pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB: u32 = 64;
pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 = 256;
pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 = 88;
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 09/32] gpu: nova-core: mm: borrow BarUser for temporary BAR1 access
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (7 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 08/32] gpu: nova-core: vgpu: reserve the 48-VM WPR2 heap Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 10/32] gpu: nova-core: mm: add VramBlock Zhi Wang
` (22 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang, Alistair Popple
Temporary BAR1 access needs a borrow of the GPU-owned BarUser. Store
BarUser inline in Gpu and borrow it in BarUserAccess, avoiding a separate
allocation and reference counting for these accesses. Update the existing
self-test entry points to accept the borrowed interface.
No functional change is intended.
Cc: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 21 +++++++++------------
drivers/gpu/nova-core/mm.rs | 5 ++---
drivers/gpu/nova-core/mm/bar_user.rs | 27 ++++++++++++---------------
3 files changed, 23 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 227531b28541..ebf29b06a8e1 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -16,7 +16,6 @@
SizeConstants,
SZ_4K, //
},
- sync::Arc,
};
use crate::{
@@ -327,7 +326,8 @@ pub(crate) struct Gpu<'gpu> {
/// the GSP is still operational.
mm: GpuMm<'gpu>,
/// BAR1 user interface for CPU access to GPU virtual memory.
- bar_user: Arc<BarUser<'gpu>>,
+ #[pin]
+ bar_user: BarUser<'gpu>,
/// GSP and its resources.
#[pin]
gsp_resources: GspResources<'gpu>,
@@ -523,19 +523,16 @@ pub(crate) fn new<'a>(
},
// Create BAR1 user interface for CPU access to GPU virtual memory.
- bar_user: {
+ bar_user <- {
let pdb_addr =
VramAddress::from_raw(gsp_resources.boot_result.static_info.bar1_pde_base);
let bar1_idx = crate::driver::bar1_resource_index(pdev)?;
let bar1_size = pdev.resource_len(bar1_idx)?;
- Arc::pin_init(
- BarUser::new(
- pdb_addr,
- gsp_resources.spec.chipset,
- bar1_size,
- bar1,
- )?,
- GFP_KERNEL,
+ BarUser::new(
+ pdb_addr,
+ gsp_resources.spec.chipset,
+ bar1_size,
+ bar1,
)?
},
})
@@ -552,7 +549,7 @@ pub(crate) fn run_selftests(self: Pin<&mut Self>, pdev: &pci::Device<device::Bou
dev,
this.mm,
regions,
- this.bar_user,
+ this.bar_user.as_ref().get_ref(),
this.gsp_resources.boot_result.static_info.bar1_pde_base,
this.gsp_resources.spec.chipset,
) {
diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs
index a5bc4042577b..8a934c55169f 100644
--- a/drivers/gpu/nova-core/mm.rs
+++ b/drivers/gpu/nova-core/mm.rs
@@ -298,8 +298,7 @@ pub(crate) mod selftest {
use kernel::{
device,
- sizes::SizeConstants,
- sync::Arc, //
+ sizes::SizeConstants, //
};
use super::*;
@@ -309,7 +308,7 @@ pub(crate) fn run(
dev: &device::Device<device::Bound>,
mm: &mut GpuMm<'_>,
usable_fb_regions: &[Range<u64>],
- bar_user: &Arc<bar_user::BarUser<'_>>,
+ bar_user: &bar_user::BarUser<'_>,
bar1_pdb: u64,
chipset: Chipset,
) -> Result {
diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs
index 1bef01d147ad..2e6d229b1a23 100644
--- a/drivers/gpu/nova-core/mm/bar_user.rs
+++ b/drivers/gpu/nova-core/mm/bar_user.rs
@@ -7,10 +7,7 @@
io::Io,
new_mutex,
prelude::*,
- sync::{
- Arc,
- Mutex, //
- },
+ sync::Mutex, //
};
use crate::{
@@ -60,12 +57,12 @@ pub(crate) fn new(
}
/// Map physical pages to a contiguous BAR1 virtual range.
- pub(crate) fn map(
- self: &Arc<Self>,
+ pub(crate) fn map<'access>(
+ &'access self,
mm: &mut GpuMm<'_>,
pfns: &[Pfn],
writable: bool,
- ) -> Result<BarUserAccess<'gpu>> {
+ ) -> Result<BarUserAccess<'access, 'gpu>> {
if pfns.is_empty() {
return Err(EINVAL);
}
@@ -73,22 +70,22 @@ pub(crate) fn map(
let mapped = vmm.map_pages(mm, pfns, None, writable)?;
Ok(BarUserAccess {
- bar_user: self.clone(),
+ bar_user: self,
mapped: Some(mapped),
})
}
}
/// Access object for a mapped BAR1 region.
-pub(crate) struct BarUserAccess<'gpu> {
- bar_user: Arc<BarUser<'gpu>>,
+pub(crate) struct BarUserAccess<'access, 'gpu> {
+ bar_user: &'access BarUser<'gpu>,
/// [`BarUserAccess::release`] [`Option::take`]s this; `Some` at
/// drop time means `release()` was never called.
mapped: Option<MappedRange>,
}
#[expect(dead_code)]
-impl BarUserAccess<'_> {
+impl BarUserAccess<'_, '_> {
/// Tear down the BAR1 mapping.
pub(crate) fn release(mut self, mm: &mut GpuMm<'_>) -> Result {
let mapped = self.mapped.take().ok_or(EINVAL)?;
@@ -162,7 +159,7 @@ pub(crate) fn try_write64(&self, value: u64, offset: usize) -> Result {
}
}
-impl Drop for BarUserAccess<'_> {
+impl Drop for BarUserAccess<'_, '_> {
fn drop(&mut self) {
if self.mapped.is_some() {
kernel::pr_warn!(
@@ -180,10 +177,10 @@ fn drop(&mut self) {
/// address space. Uses the `GpuMm`'s buddy allocator to allocate page tables
/// and test pages as needed.
#[cfg(CONFIG_NOVA_CORE_SELFTESTS)]
-pub(crate) fn run_self_test(
+pub(super) fn run_self_test(
dev: &device::Device<device::Bound>,
mm: &mut GpuMm<'_>,
- bar_user: &Arc<BarUser<'_>>,
+ bar_user: &BarUser<'_>,
bar1_pdb: u64,
chipset: Chipset,
) -> Result {
@@ -386,7 +383,7 @@ pub(crate) fn run_self_test(
drop(vmm);
// Test 4: Exercise `BarUser::map()` end-to-end.
- let bar_user = Arc::pin_init(
+ let bar_user = KBox::pin_init(
BarUser::new(pdb_addr, chipset, SZ_64K.into_safe_cast(), bar1)?,
GFP_KERNEL,
)?;
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 10/32] gpu: nova-core: mm: add VramBlock
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (8 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 09/32] gpu: nova-core: mm: borrow BarUser for temporary BAR1 access Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 11/32] gpu: nova-core: mm: add VramRegion Zhi Wang
` (21 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang, Alistair Popple
vGPU memory slots need allocations at fixed offsets within usable VRAM.
Add GpuMm::alloc_vram_range and VramBlock to own these exact allocations
and return their storage to the buddy allocator on drop.
Use the buddy allocator's range validation and retain the checks for
absolute physical address overflow and alignment.
Cc: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/mm.rs | 2 +
drivers/gpu/nova-core/mm/vram.rs | 78 ++++++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)
create mode 100644 drivers/gpu/nova-core/mm/vram.rs
diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs
index 8a934c55169f..016d99608aeb 100644
--- a/drivers/gpu/nova-core/mm.rs
+++ b/drivers/gpu/nova-core/mm.rs
@@ -67,6 +67,8 @@ macro_rules! impl_pfn_bounded {
mod regs;
pub(super) mod tlb;
pub(super) mod vmm;
+#[expect(dead_code)]
+pub(crate) mod vram;
/// GPU Memory Manager - owns all core MM components.
///
diff --git a/drivers/gpu/nova-core/mm/vram.rs b/drivers/gpu/nova-core/mm/vram.rs
new file mode 100644
index 000000000000..743a2a163318
--- /dev/null
+++ b/drivers/gpu/nova-core/mm/vram.rs
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! VRAM allocation.
+
+use core::ops::Range;
+
+use kernel::{
+ gpu::buddy::{
+ AllocatedBlocks,
+ GpuBuddyAllocFlags,
+ GpuBuddyAllocMode, //
+ },
+ prelude::*,
+ ptr::Alignment,
+ sync::Arc, //
+};
+
+use crate::num::IntoSafeCast;
+
+use super::{
+ GpuMm,
+ PAGE_SIZE, //
+};
+
+/// A physically contiguous VRAM allocation.
+pub(crate) struct VramBlock {
+ _blocks: Pin<KBox<AllocatedBlocks>>,
+ address: u64,
+ size: u64,
+}
+
+impl VramBlock {
+ pub(crate) const fn address(&self) -> u64 {
+ self.address
+ }
+}
+
+impl GpuMm<'_> {
+ /// Allocates an exact byte range relative to the buddy allocator's base.
+ pub(crate) fn alloc_vram_range(&self, range: Range<u64>, align: u64) -> Result<Arc<VramBlock>> {
+ let size = range.end.checked_sub(range.start).ok_or(EINVAL)?;
+ let align = align.max(PAGE_SIZE.into_safe_cast());
+ let min_block_size =
+ Alignment::new_checked(usize::try_from(align).map_err(|_| EOVERFLOW)?).ok_or(EINVAL)?;
+ let buddy = self.buddy();
+ let address = buddy
+ .base_offset()
+ .checked_add(range.start)
+ .ok_or(EOVERFLOW)?;
+ buddy
+ .base_offset()
+ .checked_add(range.end)
+ .ok_or(EOVERFLOW)?;
+ if !address.is_multiple_of(align) {
+ return Err(EINVAL);
+ }
+
+ let blocks = KBox::pin_init(
+ buddy.alloc_blocks(
+ GpuBuddyAllocMode::Range(range),
+ size,
+ min_block_size,
+ GpuBuddyAllocFlags::default(),
+ ),
+ GFP_KERNEL,
+ )?;
+
+ Ok(Arc::new(
+ VramBlock {
+ _blocks: blocks,
+ address,
+ size,
+ },
+ GFP_KERNEL,
+ )?)
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 11/32] gpu: nova-core: mm: add VramRegion
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (9 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 10/32] gpu: nova-core: mm: add VramBlock Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 12/32] gpu: nova-core: mm: add BarMapping Zhi Wang
` (20 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang, Alistair Popple
BAR mappings do not necessarily cover an entire VRAM block. A region
layer lets a mapping select a byte range while keeping the underlying
allocation alive.
For vGPU, communication buffers occupy only part of the management heap
and need a BAR mapping of that range.
Add VramRegion to describe ranges within a shared VramBlock and support
bounds-checked subregions.
Cc: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/mm/vram.rs | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/nova-core/mm/vram.rs b/drivers/gpu/nova-core/mm/vram.rs
index 743a2a163318..2c7183f08027 100644
--- a/drivers/gpu/nova-core/mm/vram.rs
+++ b/drivers/gpu/nova-core/mm/vram.rs
@@ -34,6 +34,68 @@ impl VramBlock {
pub(crate) const fn address(&self) -> u64 {
self.address
}
+
+ /// Creates a byte range relative to this allocation, retaining its backing storage.
+ pub(crate) fn region(self: &Arc<Self>, range: Range<u64>) -> Result<VramRegion> {
+ VramRegion::new(self.clone(), range)
+ }
+}
+
+/// A byte range that keeps its VRAM allocation alive.
+#[derive(Clone)]
+pub(crate) struct VramRegion {
+ backing: Arc<VramBlock>,
+ address: u64,
+ size: u64,
+}
+
+impl VramRegion {
+ fn new(backing: Arc<VramBlock>, range: Range<u64>) -> Result<Self> {
+ let size = range
+ .end
+ .checked_sub(range.start)
+ .filter(|size| *size != 0)
+ .ok_or(EINVAL)?;
+ if range.end > backing.size {
+ return Err(EINVAL);
+ }
+ let address = backing.address.checked_add(range.start).ok_or(EOVERFLOW)?;
+ backing.address.checked_add(range.end).ok_or(EOVERFLOW)?;
+
+ Ok(Self {
+ backing,
+ address,
+ size,
+ })
+ }
+
+ pub(crate) const fn address(&self) -> u64 {
+ self.address
+ }
+
+ pub(crate) const fn size(&self) -> u64 {
+ self.size
+ }
+
+ /// Creates a nonempty subregion relative to this view's start.
+ pub(crate) fn subregion(&self, range: Range<u64>) -> Result<Self> {
+ let size = range
+ .end
+ .checked_sub(range.start)
+ .filter(|size| *size != 0)
+ .ok_or(EINVAL)?;
+ if range.end > self.size {
+ return Err(EINVAL);
+ }
+ let address = self.address.checked_add(range.start).ok_or(EOVERFLOW)?;
+ address.checked_add(size).ok_or(EOVERFLOW)?;
+
+ Ok(Self {
+ backing: self.backing.clone(),
+ address,
+ size,
+ })
+ }
}
impl GpuMm<'_> {
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 12/32] gpu: nova-core: mm: add BarMapping
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (10 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 11/32] gpu: nova-core: mm: add VramRegion Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 13/32] gpu: nova-core: gsp: dispatch RM RPC messages during GMC receive Zhi Wang
` (19 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang, Alistair Popple
vGPU communication buffers need CPU access to regions within their
VramBlocks. Add BarMapping to map these regions through BAR1, including
regions that start or end within a page.
Use BarUserAccess for the mapping and retain the backing region until
destruction. Restrict CPU accesses to the region's byte range.
Cc: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/mm/bar_user.rs | 105 +++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs
index 2e6d229b1a23..ef357fd516b7 100644
--- a/drivers/gpu/nova-core/mm/bar_user.rs
+++ b/drivers/gpu/nova-core/mm/bar_user.rs
@@ -18,6 +18,7 @@
MappedRange,
Vmm, //
},
+ vram::VramRegion,
GpuMm,
Pfn,
Vfn,
@@ -171,6 +172,110 @@ fn drop(&mut self) {
}
}
+/// A BAR1 mapping that retains its backing VRAM region.
+///
+/// Unmapping requires [`Self::destroy`]; dropping this object does not unmap it.
+#[must_use]
+pub(crate) struct BarMapping<'map, 'gpu> {
+ access: BarUserAccess<'map, 'gpu>,
+ region: VramRegion,
+ page_bias: usize,
+ logical_size: usize,
+}
+
+#[expect(dead_code)]
+impl<'map, 'gpu> BarMapping<'map, 'gpu> {
+ /// Maps the containing pages while restricting CPU access to the requested byte range.
+ pub(crate) fn new(
+ bar_user: &'map BarUser<'gpu>,
+ mm: &mut GpuMm<'_>,
+ region: VramRegion,
+ writable: bool,
+ ) -> Result<Self> {
+ let page_size: u64 = PAGE_SIZE.into_safe_cast();
+ let region_start = region.address();
+ let region_end = region_start.checked_add(region.size()).ok_or(EOVERFLOW)?;
+ let map_start = region_start - region_start % page_size;
+ let map_end =
+ region_end.checked_add(page_size - 1).ok_or(EOVERFLOW)? / page_size * page_size;
+ let map_size = map_end.checked_sub(map_start).ok_or(EINVAL)?;
+ let num_pages = usize::try_from(map_size / page_size).map_err(|_| EOVERFLOW)?;
+ if num_pages == 0 {
+ return Err(EINVAL);
+ }
+
+ let page_bias = usize::try_from(region_start - map_start).map_err(|_| EOVERFLOW)?;
+ let logical_size = usize::try_from(region.size()).map_err(|_| EOVERFLOW)?;
+ let mut pfns = KVec::with_capacity(num_pages, GFP_KERNEL)?;
+ for page in 0..num_pages {
+ let byte_offset = u64::try_from(page)
+ .map_err(|_| EOVERFLOW)?
+ .checked_mul(page_size)
+ .ok_or(EOVERFLOW)?;
+ let address = map_start.checked_add(byte_offset).ok_or(EOVERFLOW)?;
+ pfns.push(Pfn::from(VramAddress::from_raw(address)), GFP_KERNEL)?;
+ }
+
+ let access = bar_user.map(mm, &pfns, writable)?;
+
+ Ok(Self {
+ access,
+ region,
+ page_bias,
+ logical_size,
+ })
+ }
+
+ pub(crate) fn region(&self) -> &VramRegion {
+ &self.region
+ }
+
+ pub(crate) fn gpu_va_addr(&self) -> Result<u64> {
+ self.access
+ .base()
+ .into_raw()
+ .checked_add(u64::try_from(self.page_bias).map_err(|_| EOVERFLOW)?)
+ .ok_or(EOVERFLOW)
+ }
+
+ pub(crate) const fn size(&self) -> usize {
+ self.logical_size
+ }
+
+ fn access_offset(&self, offset: usize, width: usize) -> Result<usize> {
+ let logical_end = offset.checked_add(width).ok_or(EOVERFLOW)?;
+ if logical_end > self.logical_size {
+ return Err(EINVAL);
+ }
+
+ let access_offset = self.page_bias.checked_add(offset).ok_or(EOVERFLOW)?;
+ if !access_offset.is_multiple_of(width) {
+ return Err(EINVAL);
+ }
+
+ Ok(access_offset)
+ }
+
+ pub(crate) fn try_read32(&self, offset: usize) -> Result<u32> {
+ self.access
+ .try_read32(self.access_offset(offset, size_of::<u32>())?)
+ }
+
+ pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result {
+ self.access
+ .try_write32(value, self.access_offset(offset, size_of::<u32>())?)
+ }
+
+ pub(crate) fn try_write64(&self, value: u64, offset: usize) -> Result {
+ self.access
+ .try_write64(value, self.access_offset(offset, size_of::<u64>())?)
+ }
+
+ pub(crate) fn destroy(self, mm: &mut GpuMm<'_>) -> Result {
+ self.access.release(mm)
+ }
+}
+
/// Run MM subsystem self-tests during probe.
///
/// Tests page table infrastructure and `BAR1` MMIO access using the `BAR1`
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 13/32] gpu: nova-core: gsp: dispatch RM RPC messages during GMC receive
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (11 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 12/32] gpu: nova-core: mm: add BarMapping Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 14/32] gpu: nova-core: gsp: add synchronous GMC transactions Zhi Wang
` (18 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
RM RPC notifications and GMC messages share the GSP-to-CPU queue.
GMC waits and the threaded queue drain need to recognize both formats
while preserving RM RPC notification handling.
Validate the common framing before selecting the message format, dispatch
interleaved RM RPC messages, and use the same receive path when draining
the queue.
Co-developed-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/cmdq.rs | 122 ++++++++++++++++----------
drivers/gpu/nova-core/gsp/commands.rs | 8 +-
drivers/gpu/nova-core/gsp/fw.rs | 9 ++
3 files changed, 89 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index 942f41b4d705..b7d8a467d2fe 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -602,8 +602,8 @@ pub(crate) fn send_command_no_wait<M>(&self, command: M) -> Result
self.inner.lock().send_command(command).map(|_| ())
}
- /// Receives one GMC element from the GSP and passes its command id, the `max_resp_or_status`
- /// field, and the raw payload slices to `handler`.
+ /// Receives one GMC element from the GSP and passes its header and raw payload slices to
+ /// `handler`.
///
/// This method may sleep while waiting. The [`CmdqInner`] mutex stays locked across the wait
/// and across the `handler` call, so `handler` must not call back into this [`Cmdq`].
@@ -900,6 +900,10 @@ fn wait_for_msg(&self, timeout: Delta) -> Result<GspMessage<'_>> {
)));
}
+ if !header.is_rm_rpc() {
+ return Err(self.poison(fmt!("invalid RM RPC NVDM type")));
+ }
+
dev_dbg!(
&self.dev,
"GSP RPC: receive: seq# {}, function={:?}, length=0x{:x}\n",
@@ -938,6 +942,24 @@ fn wait_for_msg(&self, timeout: Delta) -> Result<GspMessage<'_>> {
})
}
+ /// Consumes and dispatches the RM RPC element currently at the queue head.
+ fn consume_and_dispatch_rpc(&mut self) -> Result {
+ let (function, seq, length) = {
+ let message = self.wait_for_msg(Delta::ZERO)?;
+
+ (
+ message.header.function(),
+ message.header.sequence(),
+ message.header.length(),
+ )
+ };
+
+ let pages = u32::try_from(length.div_ceil(GSP_PAGE_SIZE))?;
+ DmaGspMem::advance_cpu_read_ptr_v2(self.bar, pages);
+ self.log_event(function, seq);
+ Ok(())
+ }
+
/// Receive a message from the GSP.
///
/// The expected message type is specified using the `M` generic parameter. A message whose
@@ -1087,27 +1109,21 @@ fn log_event(&self, function: Result<MsgFunction, u32>, seq: u32) {
/// Drains all messages currently pending in the GSP-to-CPU queue.
///
/// Reads whatever the GSP has already posted and stops once the queue is empty. No caller is
- /// waiting for a reply during a drain, so every message goes to [`Self::log_event`].
+ /// waiting for a reply during a drain, so RM RPC messages go to [`Self::log_event`] and GMC
+ /// messages are consumed without dispatch.
///
/// # Errors
///
/// Returns the receive error that stopped the drain, in particular the `EIO` of a queue
- /// poisoned by corrupt framing (see [`Self::wait_for_msg`]).
+ /// poisoned by corrupt framing (see [`Self::receive_gmc_and_dispatch`]).
fn drain(&mut self) -> Result {
while !self.gsp_mem.driver_read_area_v2(self.bar).0.is_empty() {
- // A message is available, so this returns without waiting.
- let msg = self.wait_for_msg(Delta::ZERO)?;
-
- let pages =
- u32::try_from(msg.header.length().div_ceil(GSP_PAGE_SIZE)).map_err(|_| {
- dev_err!(&self.dev, "GSP drain: message length overflow\n");
- EIO
- })?;
- let function = msg.header.function();
- let seq = msg.header.sequence();
-
- DmaGspMem::advance_cpu_read_ptr_v2(self.bar, pages);
- self.log_event(function, seq);
+ match self.receive_gmc_and_dispatch::<()>(Delta::ZERO, |_, _, _| {
+ (None, QueuePointers::Unchanged)
+ }) {
+ Ok(_) | Err(ERANGE) => {}
+ Err(error) => return Err(error),
+ }
}
Ok(())
@@ -1145,7 +1161,14 @@ fn wait_for_gmc_msg(&self, timeout: Delta) -> Result<GmcMessage<'_>> {
return Err(EIO);
};
- if let Err(e) = header.validate_framing() {
+ let framing = header.validate_common_framing().and_then(|()| {
+ if header.is_gmc_api() {
+ header.validate_framing()
+ } else {
+ Ok(())
+ }
+ });
+ if let Err(e) = framing {
dev_err!(
&self.dev,
"GSP GMC: receive: bad MCTP framing, declared length {}\n",
@@ -1182,29 +1205,34 @@ fn wait_for_gmc_msg(&self, timeout: Delta) -> Result<GmcMessage<'_>> {
})
}
- /// Receive the next GMC event from the GSP and dispatch it through a handler.
+ /// Receive the next GMC element from the GSP and dispatch it through a handler.
///
- /// The handler receives the GMC command id, the raw payload slices that follow the
- /// [`super::fw::GmcApiHeader`] (two because the ring may wrap), and that header's
+ /// The handler receives the message header and the raw payload slices that follow the
+ /// [`super::fw::GmcApiHeader`] (two because the ring may wrap). The header contains the
/// `max_resp_or_status` field, which only a handler that knows what it asked for can read.
/// It returns `None` for an element it does not handle, paired with the [`QueuePointers`]
/// state it left behind.
///
- /// Returns `Ok(None)` when nothing claimed the element, either because it is not a GMC
- /// element or because the handler declined it. Either way the element is consumed: the read
- /// pointer moves past it, or is written back past it when the handler reset the GSP.
+ /// Returns `Ok(None)` when the handler declines a GMC element. A valid interleaved RM RPC
+ /// element is consumed and dispatched before this method returns `ERANGE`. The read
+ /// pointer moves past the element, or is written back past it when the handler reset the GSP.
///
/// # Errors
///
/// - `ETIMEDOUT` if `timeout` has elapsed before any message becomes available.
/// - `EIO` if the queue is poisoned or the element fails framing validation (see
/// [`Self::wait_for_gmc_msg`]).
+ /// - `ERANGE` if a valid interleaved RM RPC element was consumed and dispatched.
fn receive_gmc_and_dispatch<R>(
&mut self,
timeout: Delta,
handler: impl FnOnce(&GspGmcMsgElement, &[u8], &[u8]) -> (Option<R>, QueuePointers),
) -> Result<Option<R>> {
let message = self.wait_for_gmc_msg(timeout)?;
+ if !message.header.is_gmc_api() {
+ self.consume_and_dispatch_rpc()?;
+ return Err(ERANGE);
+ }
let header = message.header;
let length = header.length();
@@ -1213,32 +1241,30 @@ fn receive_gmc_and_dispatch<R>(
let cpu_write_ptr = DmaGspMem::cpu_write_ptr_v2(self.bar);
let cpu_read_ptr = DmaGspMem::cpu_read_ptr_v2(self.bar);
- let (result, queue_pointers) = if !header.is_gmc_api() {
- dev_warn!(&self.dev, "GSP GMC: dropping non-GMC queue element\n");
- (None, QueuePointers::Unchanged)
- } else if num::u32_as_usize(header.gmc.size) != header.payload_length() {
- // GSP-RM sends the element as the GMC header plus `size` bytes, so the two lengths
- // describe the same payload and a handler cannot tell which one to believe.
- dev_err!(
- &self.dev,
- "GSP GMC: payload is {} bytes, transport declares {}\n",
- header.gmc.size,
- header.payload_length(),
- );
- (None, QueuePointers::Unchanged)
- } else {
- let command_id = header.gmc.command_id();
+ let (result, queue_pointers) =
+ if num::u32_as_usize(header.gmc.size) != header.payload_length() {
+ // GSP-RM sends the element as the GMC header plus `size` bytes, so the two lengths
+ // describe the same payload and a handler cannot tell which one to believe.
+ dev_err!(
+ &self.dev,
+ "GSP GMC: payload is {} bytes, transport declares {}\n",
+ header.gmc.size,
+ header.payload_length(),
+ );
+ (None, QueuePointers::Unchanged)
+ } else {
+ let command_id = header.gmc.command_id();
- dev_dbg!(
- &self.dev,
- "GSP GMC: event: seq# {}, command_id=0x{:x}, length=0x{:x}\n",
- header.gmc.sequence,
- command_id,
- length,
- );
+ dev_dbg!(
+ &self.dev,
+ "GSP GMC: event: seq# {}, command_id=0x{:x}, length=0x{:x}\n",
+ header.gmc.sequence,
+ command_id,
+ length,
+ );
- handler(header, message.contents.0, message.contents.1)
- };
+ handler(header, message.contents.0, message.contents.1)
+ };
let pages = u32::try_from(length.div_ceil(GSP_PAGE_SIZE))?;
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index c2faa825a849..7ca5ec2a58d9 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -209,7 +209,7 @@ pub(crate) fn gsp_init(
cmdq.send_gmc_no_wait(GMCAPI_CMD_GSP_INIT, payload, GSP_INIT_MAX_RESPONSE_SIZE)?;
loop {
- let reply = cmdq.receive_gmc_and_dispatch(
+ let reply = match cmdq.receive_gmc_and_dispatch(
Cmdq::RECEIVE_TIMEOUT,
|header, payload_0, payload_1| {
if header.is_response_to(GMCAPI_CMD_GSP_INIT, sequence) {
@@ -231,7 +231,11 @@ pub(crate) fn gsp_init(
}
}
},
- )?;
+ ) {
+ Ok(reply) => reply,
+ Err(ERANGE) => continue,
+ Err(error) => return Err(error),
+ };
if let Some(reply) = reply {
return reply;
diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs
index 309f9296ebc8..0fccf16f6a1c 100644
--- a/drivers/gpu/nova-core/gsp/fw.rs
+++ b/drivers/gpu/nova-core/gsp/fw.rs
@@ -527,6 +527,11 @@ pub(crate) fn validate_framing(&self) -> Result {
self.transport.validate(size_of::<Self>())
}
+ /// Returns `true` if the NVDM header routes this element to the RM RPC dispatcher.
+ pub(super) fn is_rm_rpc(&self) -> bool {
+ self.transport.is_nvdm_type(NvdmType::RmRpc)
+ }
+
// Returns the sequence number of the message.
pub(crate) fn sequence(&self) -> u32 {
self.rpc.sequence
@@ -811,6 +816,10 @@ pub(crate) fn validate_framing(&self) -> Result {
self.transport.validate(size_of::<Self>())
}
+ pub(super) fn validate_common_framing(&self) -> Result {
+ self.transport.validate(size_of::<QueueElementHeader>())
+ }
+
/// Returns `true` if the NVDM type says a GMC header follows the transport header.
///
/// When it returns `false`, `gmc` holds whatever header the other element kind puts there.
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 14/32] gpu: nova-core: gsp: add synchronous GMC transactions
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (12 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 13/32] gpu: nova-core: gsp: dispatch RM RPC messages during GMC receive Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 15/32] gpu: nova-core: gsp: add status-only " Zhi Wang
` (17 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
vGPU management queries return data that callers decode after the receive
queue slot is released. The request and response must also remain within
one transaction so another receiver cannot consume the reply.
Hold the queue lock across send and receive, match the response flag,
command ID and sequence, and return the status with an owned payload.
Support default and caller-selected response timeouts.
Co-developed-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/cmdq.rs | 98 +++++++++++++++++++++++++++++++
drivers/gpu/nova-core/gsp/fw.rs | 8 ++-
2 files changed, 103 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index b7d8a467d2fe..9fb17e576eb8 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -500,6 +500,16 @@ pub(crate) enum QueuePointers {
Reset,
}
+/// Response from a GMC API command.
+pub(crate) struct GmcResponse {
+ /// Response status (`NV_STATUS` code). Zero means success.
+ #[expect(dead_code)]
+ pub(crate) status: u32,
+ /// Response payload copied out of the message queue.
+ #[expect(dead_code)]
+ pub(crate) payload: KVec<u8>,
+}
+
/// GSP command queue.
///
/// Provides the ability to send commands and receive messages from the GSP using a shared memory
@@ -638,6 +648,94 @@ pub(crate) fn send_gmc_no_wait(
.send_gmc(command_id, payload, max_response_size)
}
+ /// Sends a GMC API command and waits for its matching response.
+ ///
+ /// The queue stays locked for the complete transaction. A single deadline bounds all queue
+ /// elements observed while waiting.
+ #[expect(dead_code)]
+ pub(crate) fn send_gmc_and_receive(
+ &self,
+ command_id: u32,
+ payload: &[u8],
+ max_response_size: u32,
+ ) -> Result<GmcResponse> {
+ self.send_gmc_and_receive_timeout(
+ command_id,
+ payload,
+ max_response_size,
+ Self::RECEIVE_TIMEOUT,
+ )
+ }
+
+ /// Sends a GMC API command and waits up to `timeout` for its matching response.
+ pub(crate) fn send_gmc_and_receive_timeout(
+ &self,
+ command_id: u32,
+ payload: &[u8],
+ max_response_size: u32,
+ timeout: Delta,
+ ) -> Result<GmcResponse> {
+ let mut inner = self.inner.lock();
+ let expected_sequence = inner.send_gmc(command_id, payload, max_response_size)?;
+ let dev = inner.dev;
+
+ let deadline = Instant::<Monotonic>::now() + timeout;
+ loop {
+ let remaining = deadline - Instant::<Monotonic>::now();
+ if remaining.is_negative() {
+ return Err(ETIMEDOUT);
+ }
+
+ let response =
+ match inner.receive_gmc_and_dispatch(remaining, |header, payload_0, payload_1| {
+ let header = &header.gmc;
+ if !header.is_response_to(command_id, expected_sequence) {
+ let kind = if header.is_response() {
+ "response"
+ } else {
+ "event"
+ };
+ dev_dbg!(
+ dev,
+ "GSP GMC: skip {} seq {} cmd {:#x}; want response seq {} cmd {:#x}\n",
+ kind,
+ header.sequence,
+ header.command_id(),
+ expected_sequence,
+ command_id,
+ );
+ return (None, QueuePointers::Unchanged);
+ }
+
+ let response: Result<GmcResponse> = (|| {
+ let mut payload = KVec::with_capacity(
+ payload_0
+ .len()
+ .checked_add(payload_1.len())
+ .ok_or(EOVERFLOW)?,
+ GFP_KERNEL,
+ )?;
+ payload.extend_from_slice(payload_0, GFP_KERNEL)?;
+ payload.extend_from_slice(payload_1, GFP_KERNEL)?;
+ Ok(GmcResponse {
+ status: header.max_resp_or_status,
+ payload,
+ })
+ })();
+
+ (Some(response), QueuePointers::Unchanged)
+ }) {
+ Ok(response) => response,
+ Err(ERANGE) => continue,
+ Err(error) => return Err(error),
+ };
+
+ if let Some(response) = response {
+ return response;
+ }
+ }
+ }
+
/// Waits for an unsolicited GSP event of type `M`, consuming any other event that arrives
/// first.
///
diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs
index 0fccf16f6a1c..ac94fb564bfd 100644
--- a/drivers/gpu/nova-core/gsp/fw.rs
+++ b/drivers/gpu/nova-core/gsp/fw.rs
@@ -739,13 +739,15 @@ pub(crate) fn command_id(&self) -> u32 {
}
/// Returns `true` if GSP-RM sent this header as a response rather than an event.
- fn is_response(&self) -> bool {
+ pub(super) fn is_response(&self) -> bool {
self.command & GMCAPI_COMMAND_FLAGS_RESPONSE != 0
}
/// Returns `true` if this header answers the request that sent `command_id` under `sequence`.
- fn is_response_to(&self, command_id: u32, sequence: u64) -> bool {
- self.is_response() && self.command_id() == command_id && self.sequence == sequence
+ pub(super) fn is_response_to(&self, command_id: u32, sequence: u64) -> bool {
+ self.is_response()
+ && self.command_id() == (command_id & GMCAPI_COMMAND_ID_MASK)
+ && self.sequence == sequence
}
}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 15/32] gpu: nova-core: gsp: add status-only GMC transactions
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (13 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 14/32] gpu: nova-core: gsp: add synchronous GMC transactions Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 16/32] gpu: nova-core: gsp: wait for GMC completion events Zhi Wang
` (16 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GMC operations such as GSP plugin resource cleanup have no response
payload, but still report success or failure in the response header.
Add a helper that waits for the matching response with a zero payload
limit and converts a nonzero firmware status to EIO.
Co-developed-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/cmdq.rs | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index 9fb17e576eb8..891dec5c108a 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -503,7 +503,6 @@ pub(crate) enum QueuePointers {
/// Response from a GMC API command.
pub(crate) struct GmcResponse {
/// Response status (`NV_STATUS` code). Zero means success.
- #[expect(dead_code)]
pub(crate) status: u32,
/// Response payload copied out of the message queue.
#[expect(dead_code)]
@@ -652,7 +651,6 @@ pub(crate) fn send_gmc_no_wait(
///
/// The queue stays locked for the complete transaction. A single deadline bounds all queue
/// elements observed while waiting.
- #[expect(dead_code)]
pub(crate) fn send_gmc_and_receive(
&self,
command_id: u32,
@@ -736,6 +734,17 @@ pub(crate) fn send_gmc_and_receive_timeout(
}
}
+ /// Sends a synchronous GMC command and checks its status-only reply.
+ #[expect(dead_code)]
+ pub(crate) fn send_gmc_and_check_status(&self, command_id: u32, payload: &[u8]) -> Result {
+ let response = self.send_gmc_and_receive(command_id, payload, 0)?;
+ if response.status == 0 {
+ Ok(())
+ } else {
+ Err(EIO)
+ }
+ }
+
/// Waits for an unsolicited GSP event of type `M`, consuming any other event that arrives
/// first.
///
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 16/32] gpu: nova-core: gsp: wait for GMC completion events
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (14 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 15/32] gpu: nova-core: gsp: add status-only " Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 17/32] gpu: nova-core: vgpu: add r000 plugin bindings Zhi Wang
` (15 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
GSP plugin shutdown completes through a separate event carrying the
GFID. Releasing the queue lock between sending and waiting allows another
receiver to consume that completion.
Hold the lock until the caller's predicate matches the completion event.
Pass unmatched GMC events to the caller and keep one receive deadline
while processing interleaved traffic.
Co-developed-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/cmdq.rs | 61 +++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index 891dec5c108a..137242ca0b11 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -745,6 +745,67 @@ pub(crate) fn send_gmc_and_check_status(&self, command_id: u32, payload: &[u8])
}
}
+ /// Sends an asynchronous GMC command and waits atomically for its event.
+ ///
+ /// The command queue remains locked from the send through the matching
+ /// event, preventing another transaction from consuming its completion.
+ /// Interleaved GMC events are passed to `handler`; responses are consumed
+ /// while waiting. The receive deadline starts after sending.
+ ///
+ /// Both callbacks run with the queue locked and must not reenter this queue or reset it.
+ /// Their second argument is the raw `max_resp_or_status` word of the event header.
+ #[expect(dead_code)]
+ pub(crate) fn send_gmc_and_wait_event(
+ &self,
+ command_id: u32,
+ payload: &[u8],
+ timeout: Delta,
+ mut predicate: impl FnMut(u32, u32, u64, &[u8], &[u8]) -> Result<bool>,
+ mut handler: impl FnMut(u32, u32, u64, &[u8], &[u8]) -> Result,
+ ) -> Result {
+ let mut inner = self.inner.lock();
+ inner.send_gmc(command_id, payload, 0)?;
+ let deadline = Instant::<Monotonic>::now() + timeout;
+
+ loop {
+ let remaining = deadline - Instant::<Monotonic>::now();
+ if remaining.is_negative() {
+ return Err(ETIMEDOUT);
+ }
+
+ let matched =
+ match inner.receive_gmc_and_dispatch(remaining, |header, payload_0, payload_1| {
+ let header = &header.gmc;
+ let result: Result<bool> = (|| {
+ if header.is_response() {
+ return Ok(false);
+ }
+
+ let command = header.command_id();
+ let max_resp_or_status = header.max_resp_or_status;
+ let sequence = header.sequence;
+ if predicate(command, max_resp_or_status, sequence, payload_0, payload_1)? {
+ return Ok(true);
+ }
+
+ handler(command, max_resp_or_status, sequence, payload_0, payload_1)?;
+ Ok(false)
+ })();
+ (Some(result), QueuePointers::Unchanged)
+ }) {
+ Ok(matched) => matched,
+ Err(ERANGE) => continue,
+ Err(error) => return Err(error),
+ };
+
+ if let Some(matched) = matched {
+ if matched? {
+ return Ok(());
+ }
+ }
+ }
+ }
+
/// Waits for an unsolicited GSP event of type `M`, consuming any other event that arrives
/// first.
///
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 17/32] gpu: nova-core: vgpu: add r000 plugin bindings
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (15 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 16/32] gpu: nova-core: gsp: wait for GMC completion events Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 18/32] gpu: nova-core: vgpu: add VRAM slot allocator Zhi Wang
` (14 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The GSP plugin communication area and RPC protocol are defined by the r000
firmware interface. Keeping local copies of that ABI risks letting the vGPU
manager drift from the firmware layout.
Extend the existing r000 binding set with the nova-core subset of
dev_vgpu_gsp_shared.h. The bindings expose the control and response
region types, message IDs, and firmware-defined region sizes. Keep the
raw declarations private and expose only the symbols needed by the GSP
plugin communication layer.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
.../gpu/nova-core/gsp/fw/r000_00/bindings.rs | 173 ++++++++++++++++++
1 file changed, 173 insertions(+)
diff --git a/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs b/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
index fa17d3e2edf6..3cc718bb2ab8 100644
--- a/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
+++ b/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#[repr(C)]
#[derive(Default)]
@@ -850,3 +851,175 @@ fn default() -> Self {
}
}
}
+pub const GSP_PLUGIN_BOOTLOADED: u32 = 1315261039;
+pub const VGPU_CPU_GSP_CTRL_BUFF_VERSION: u32 = 2;
+pub const VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE: u32 = 4096;
+pub const VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE: u32 = 4096;
+pub const VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE: u32 = 4096;
+pub const VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE: u32 = 2097152;
+pub const VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE: u32 = 4096;
+pub const VGPU_CPU_GSP_INIT_TASK_LOG_BUFF_REGION_SIZE: u32 = 131072;
+pub const VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE: u32 = 262144;
+pub const VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE: u32 = 65536;
+pub const VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE: u32 = 65536;
+pub const VGPU_CPU_GSP_COMMUNICATION_BUFF_TOTAL_SIZE: u32 = 2637824;
+pub type VGPU_CPU_GSP_BOOL = u32_;
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
+pub struct VGPU_CPU_GSP_VGX_VERSION {
+ pub major_number: u32_,
+ pub minor_number: u32_,
+}
+#[repr(C)]
+#[derive(Debug, Copy, Clone, MaybeZeroable)]
+pub struct VGPU_CPU_GSP_GUEST_INFO {
+ pub vgx_version: VGPU_CPU_GSP_VGX_VERSION,
+ pub guest_driver_version_buffer_length: u32_,
+ pub guest_version_buffer_length: u32_,
+ pub guest_title_buffer_length: u32_,
+ pub guest_changelist_number: u32_,
+ pub guest_driver_version_buffer: [ffi::c_char; 256usize],
+ pub guest_version_buffer: [ffi::c_char; 256usize],
+ pub guest_title_buffer: [ffi::c_char; 256usize],
+ pub guest_branch_buffer: [ffi::c_char; 256usize],
+}
+impl Default for VGPU_CPU_GSP_GUEST_INFO {
+ fn default() -> Self {
+ let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
+ unsafe {
+ ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
+ s.assume_init()
+ }
+ }
+}
+#[repr(C)]
+#[derive(Copy, Clone, MaybeZeroable)]
+pub union VGPU_CPU_GSP_CTRL_BUFF_REGION {
+ pub buf: [u8_; 4096usize],
+ pub __bindgen_anon_1: VGPU_CPU_GSP_CTRL_BUFF_REGION__bindgen_ty_1,
+}
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
+pub struct VGPU_CPU_GSP_CTRL_BUFF_REGION__bindgen_ty_1 {
+ pub version: u32_,
+ pub message_type: u32_,
+ pub message_seq_num: u32_,
+ pub __bindgen_padding_0: [u8; 4usize],
+ pub response_buff_offset: u64_,
+ pub message_buff_offset: u64_,
+ pub migration_buff_offset: u64_,
+ pub error_buff_offset: u64_,
+ pub guest_rpc_trace_buff_offset: u64_,
+ pub migration_buf_cpu_access_offset: u32_,
+ pub is_migration_in_progress: u8_,
+ pub __bindgen_padding_1: [u8; 3usize],
+ pub error_buff_cpu_get_idx: u32_,
+ pub guest_rpc_trace_buff_cpu_get_idx: u32_,
+ pub attached_vgpu_count: u32_,
+ pub is_gr_init_done: u8_,
+ pub __bindgen_padding_2: [u8; 3usize],
+ pub host_info: [VGPU_CPU_GSP_CTRL_BUFF_REGION__bindgen_ty_1__bindgen_ty_1; 16usize],
+}
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
+pub struct VGPU_CPU_GSP_CTRL_BUFF_REGION__bindgen_ty_1__bindgen_ty_1 {
+ pub vgpu_type_id: u32_,
+ pub host_gpu_pci_id: u32_,
+ pub pci_dev_id: u32_,
+ pub vgpu_uuid: [u8_; 16usize],
+}
+impl Default for VGPU_CPU_GSP_CTRL_BUFF_REGION {
+ fn default() -> Self {
+ let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
+ unsafe {
+ ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
+ s.assume_init()
+ }
+ }
+}
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_VERSION_NEGOTIATION: MESSAGE = 1;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_SETUP_CONFIG_PARAMS_AND_INIT: MESSAGE = 2;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_RESET: MESSAGE = 3;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_STOP_WORK: MESSAGE = 4;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_CANCEL_STOP: MESSAGE = 5;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_SAVE_STATE: MESSAGE = 6;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_CANCEL_SAVE: MESSAGE = 7;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_RESTORE_STATE: MESSAGE = 8;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_RESTORE_DEFERRED_STATE: MESSAGE = 9;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MIGRATION_RESUME_WORK: MESSAGE = 10;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_CONSOLE_VNC_STATE: MESSAGE = 11;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_VF_BAR0_REG_ACCESS: MESSAGE = 12;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_UPDATE_BME_STATE: MESSAGE = 13;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_RESET_MIGRATION_BUFFER_PTR: MESSAGE = 14;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_RELEASE_CLIENT_DATABASE: MESSAGE = 15;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_CHECK_IS_ALIVE: MESSAGE = 16;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_SEND_STATIC_INFO: MESSAGE = 17;
+pub const MESSAGE_NV_VGPU_CPU_RPC_MSG_MAX: MESSAGE = 18;
+pub type MESSAGE = ffi::c_uint;
+#[repr(C)]
+#[derive(Debug, Default, Copy, Clone, MaybeZeroable)]
+pub struct VGPU_CPU_GSP_DISPLAYLESS_SURFACE {
+ pub sequence_update_start: u64_,
+ pub sequence_update_end: u64_,
+ pub effective_fb_page_size: u32_,
+ pub rect_width: u32_,
+ pub rect_height: u32_,
+ pub surface_width: u32_,
+ pub surface_height: u32_,
+ pub surface_size: u32_,
+ pub surface_offset: u32_,
+ pub surface_format: u32_,
+ pub surface_kind: u32_,
+ pub surface_pitch: u32_,
+ pub surface_type: u32_,
+ pub surface_block_height: u8_,
+ pub __bindgen_padding_0: [u8; 3usize],
+ pub is_blanking_enabled: VGPU_CPU_GSP_BOOL,
+ pub is_flip_pending: VGPU_CPU_GSP_BOOL,
+ pub is_free_pending: VGPU_CPU_GSP_BOOL,
+ pub is_memory_blocklinear: VGPU_CPU_GSP_BOOL,
+}
+#[repr(C)]
+#[derive(Copy, Clone, MaybeZeroable)]
+pub union VGPU_CPU_GSP_RESPONSE_BUFF_REGION {
+ pub buf: [u8_; 4096usize],
+ pub __bindgen_anon_1: VGPU_CPU_GSP_RESPONSE_BUFF_REGION__bindgen_ty_1,
+}
+#[repr(C)]
+#[derive(Debug, Copy, Clone, MaybeZeroable)]
+pub struct VGPU_CPU_GSP_RESPONSE_BUFF_REGION__bindgen_ty_1 {
+ pub message_seq_num_received: u32_,
+ pub message_seq_num_processed: u32_,
+ pub result_code: u32_,
+ pub guest_rpc_version: u32_,
+ pub migration_buf_gsp_access_offset: u32_,
+ pub migration_state_save_complete: u32_,
+ pub is_migration_allowed: VGPU_CPU_GSP_BOOL,
+ pub __bindgen_padding_0: [u8; 4usize],
+ pub surface: [VGPU_CPU_GSP_DISPLAYLESS_SURFACE; 4usize],
+ pub error_buff_gsp_put_idx: u32_,
+ pub grid_license_state: u32_,
+ pub guest_os_type: u32_,
+ pub frl_config: u32_,
+ pub guest_info: VGPU_CPU_GSP_GUEST_INFO,
+ pub is_guest_info_populated: VGPU_CPU_GSP_BOOL,
+ pub guest_rpc_trace_buff_gsp_put_idx: u32_,
+}
+impl Default for VGPU_CPU_GSP_RESPONSE_BUFF_REGION__bindgen_ty_1 {
+ fn default() -> Self {
+ let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
+ unsafe {
+ ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
+ s.assume_init()
+ }
+ }
+}
+impl Default for VGPU_CPU_GSP_RESPONSE_BUFF_REGION {
+ fn default() -> Self {
+ let mut s = ::core::mem::MaybeUninit::<Self>::uninit();
+ unsafe {
+ ::core::ptr::write_bytes(s.as_mut_ptr(), 0, 1);
+ s.assume_init()
+ }
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 18/32] gpu: nova-core: vgpu: add VRAM slot allocator
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (16 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 17/32] gpu: nova-core: vgpu: add r000 plugin bindings Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 19/32] gpu: nova-core: gsp: factor out NVKV payload conversion Zhi Wang
` (13 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
From: Alok Kumar <alkumar@nvidia.com>
A vGPU type specifies the guest VRAM and GSP plugin management-heap
sizes for each instance. Allocating these regions independently fragments
VRAM and does not preserve a stable layout for the vGPU type.
Add a standalone slot allocator that reserves one exact VRAM range and
tracks assignments in a bitmap. Validate the vGPU type's layout and reject
an allocation request whose layout differs from the active pool.
Lay out all guest VRAM slots first and all management-heap slots
second, pairing them by bitmap index. Require the guest VRAM stride and
pool base to satisfy the required VMMU-segment alignment.
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Co-developed-by: Zhi Wang <zhiw@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/vgpu.rs | 1 +
drivers/gpu/nova-core/vgpu/vram.rs | 146 +++++++++++++++++++++++++++++
2 files changed, 147 insertions(+)
create mode 100644 drivers/gpu/nova-core/vgpu/vram.rs
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 348af9ea3fc2..6a876f8539f0 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -21,6 +21,7 @@
};
mod hal;
+mod vram;
/// vGPU state detected during GPU construction.
#[derive(Debug, Clone, Copy)]
diff --git a/drivers/gpu/nova-core/vgpu/vram.rs b/drivers/gpu/nova-core/vgpu/vram.rs
new file mode 100644
index 000000000000..2dc751b28ae3
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/vram.rs
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! VRAM slot allocation for vGPU instances.
+
+#![expect(dead_code)]
+
+use kernel::{
+ bitmap::BitmapVec,
+ prelude::*,
+ sync::Arc, //
+};
+
+use crate::mm::{
+ vram::{
+ VramBlock,
+ VramRegion, //
+ },
+ GpuMm, //
+};
+
+const VRAM_SLOT_MIN_ALIGN: u64 = 4096;
+
+#[derive(Clone, Copy, PartialEq)]
+pub(super) struct VgpuVramLayout {
+ pub(super) type_id: u32,
+ pub(super) max_slots: u32,
+ pub(super) fb_size: u64,
+ pub(super) heap_size: u64,
+ pub(super) fb_align: u64,
+}
+
+impl VgpuVramLayout {
+ fn validated(mut self) -> Result<Self> {
+ if self.max_slots == 0 || self.fb_size == 0 || self.heap_size == 0 {
+ return Err(EINVAL);
+ }
+ self.fb_align = core::cmp::max(self.fb_align, VRAM_SLOT_MIN_ALIGN);
+ if !self.fb_align.is_power_of_two() {
+ return Err(EINVAL);
+ }
+ if self.fb_size & (self.fb_align - 1) != 0
+ || self.heap_size & (VRAM_SLOT_MIN_ALIGN - 1) != 0
+ {
+ return Err(EINVAL);
+ }
+ Ok(self)
+ }
+}
+
+/// Dropping a slot does not release its reservation.
+#[must_use]
+pub(super) struct VgpuVramSlot {
+ index: usize,
+ pub(super) fbmem: VramRegion,
+ pub(super) mgmt_heap: VramRegion,
+}
+
+impl VgpuVramSlot {
+ /// Return this slot's index in the allocation pool for its vGPU type.
+ pub(super) const fn index(&self) -> usize {
+ self.index
+ }
+}
+
+pub(super) struct VgpuVramSlotAllocator {
+ backing: Arc<VramBlock>,
+ layout: VgpuVramLayout,
+ fb_region_size: u64,
+ used: BitmapVec,
+}
+
+impl VgpuVramSlotAllocator {
+ pub(super) fn new(mm: &GpuMm<'_>, layout: VgpuVramLayout) -> Result<Self> {
+ let layout = layout.validated()?;
+ let max_slots = u64::from(layout.max_slots);
+ // Keep guest VRAM slots contiguous so each starts at `fb_align`;
+ // interleaving page-aligned heaps could misalign later slots.
+ let fb_region_size = layout.fb_size.checked_mul(max_slots).ok_or(EINVAL)?;
+ let heap_region_size = layout.heap_size.checked_mul(max_slots).ok_or(EINVAL)?;
+ let pool_size = fb_region_size.checked_add(heap_region_size).ok_or(EINVAL)?;
+
+ let used = BitmapVec::new(
+ usize::try_from(layout.max_slots).map_err(|_| EINVAL)?,
+ GFP_KERNEL,
+ )?;
+ let backing = mm.alloc_vram_range(0..pool_size, VRAM_SLOT_MIN_ALIGN)?;
+ if !backing.address().is_multiple_of(layout.fb_align) {
+ return Err(EINVAL);
+ }
+
+ Ok(Self {
+ backing,
+ layout,
+ fb_region_size,
+ used,
+ })
+ }
+
+ pub(super) fn matches_layout(&self, layout: VgpuVramLayout) -> Result<bool> {
+ Ok(self.layout == layout.validated()?)
+ }
+
+ pub(super) fn alloc(&mut self, layout: VgpuVramLayout) -> Result<VgpuVramSlot> {
+ if !self.matches_layout(layout)? {
+ return Err(EBUSY);
+ }
+
+ let bitmap_index = self.used.next_zero_bit(0).ok_or(ENOSPC)?;
+ let slot = u64::try_from(bitmap_index).map_err(|_| EINVAL)?;
+ let fb_offset = self.layout.fb_size.checked_mul(slot).ok_or(EINVAL)?;
+ let fb_end = fb_offset.checked_add(self.layout.fb_size).ok_or(EINVAL)?;
+ let heap_offset = self
+ .fb_region_size
+ .checked_add(self.layout.heap_size.checked_mul(slot).ok_or(EINVAL)?)
+ .ok_or(EINVAL)?;
+ let heap_end = heap_offset
+ .checked_add(self.layout.heap_size)
+ .ok_or(EINVAL)?;
+ let fbmem = self.backing.region(fb_offset..fb_end)?;
+ let mgmt_heap = self.backing.region(heap_offset..heap_end)?;
+
+ self.used.set_bit(bitmap_index);
+
+ Ok(VgpuVramSlot {
+ index: bitmap_index,
+ fbmem,
+ mgmt_heap,
+ })
+ }
+
+ /// Drop a slot's region views and return its reservation to this pool.
+ ///
+ /// The slot must come from this allocator. All accesses and mappings of its
+ /// regions must end before releasing it.
+ pub(super) fn release(&mut self, slot: VgpuVramSlot) {
+ let index = slot.index;
+ debug_assert_eq!(self.used.next_bit(index), Some(index));
+ drop(slot);
+ self.used.clear_bit(index);
+ }
+
+ pub(super) fn is_empty(&self) -> bool {
+ self.used.last_bit().is_none()
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 19/32] gpu: nova-core: gsp: factor out NVKV payload conversion
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (17 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 18/32] gpu: nova-core: vgpu: add VRAM slot allocator Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 20/32] gpu: nova-core: vgpu: query VF assignments and properties Zhi Wang
` (12 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
Both GSP initialization and vGPU property queries decode their replies as
NVKV streams.
Move the byte-to-word conversion helper into the NVKV module and make
that module accessible to the vGPU firmware interface.
No functional change is intended.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp.rs | 2 +-
drivers/gpu/nova-core/gsp/commands.rs | 24 +-----------------------
drivers/gpu/nova-core/gsp/nvkv.rs | 24 ++++++++++++++++++++++++
3 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs
index 93291c67d6de..5b1e4eb7cad8 100644
--- a/drivers/gpu/nova-core/gsp.rs
+++ b/drivers/gpu/nova-core/gsp.rs
@@ -24,7 +24,7 @@
pub(crate) mod cmdq;
pub(crate) mod commands;
mod fw;
-mod nvkv;
+pub(crate) mod nvkv;
mod regs;
pub(crate) use fw::{
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 7ca5ec2a58d9..7945a191bd08 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -33,6 +33,7 @@
GMCAPI_CMD_GSP_SUSPEND, //
},
nvkv::{
+ nvkv_words,
Decoder,
Encodable,
EncodedStream,
@@ -41,7 +42,6 @@
},
GspBootContext,
},
- sbuffer::SBufferIter,
vgpu::VgpuState, //
};
@@ -256,28 +256,6 @@ fn decode_gsp_init_reply(
decode_gsp_info(&nvkv_words(payload_0, payload_1)?)
}
-/// Joins the two halves of a wrapped payload into the `u64` words an NVKV stream is made of.
-///
-/// # Errors
-///
-/// - `EIO` if the combined length is not a whole number of words.
-/// - `ENOMEM` if the buffer cannot be allocated.
-fn nvkv_words(payload_0: &[u8], payload_1: &[u8]) -> Result<KVVec<u64>> {
- let bytes = SBufferIter::new_reader([payload_0, payload_1]).flush_into_kvec(GFP_KERNEL)?;
- let words = bytes.chunks_exact(size_of::<u64>());
- if !words.remainder().is_empty() {
- return Err(EIO);
- }
-
- let mut out = KVVec::with_capacity(bytes.len() / size_of::<u64>(), GFP_KERNEL)?;
- for word in words {
- let word: [u8; size_of::<u64>()] = word.try_into().map_err(|_| EIO)?;
- out.push(u64::from_le_bytes(word), GFP_KERNEL)?;
- }
-
- Ok(out)
-}
-
/// Decodes the static GPU configuration from an NVKV stream.
///
/// # Errors
diff --git a/drivers/gpu/nova-core/gsp/nvkv.rs b/drivers/gpu/nova-core/gsp/nvkv.rs
index e7a9549919fb..9f2119b98b26 100644
--- a/drivers/gpu/nova-core/gsp/nvkv.rs
+++ b/drivers/gpu/nova-core/gsp/nvkv.rs
@@ -27,6 +27,30 @@
};
use zerocopy::Immutable;
+use crate::sbuffer::SBufferIter;
+
+/// Joins the two halves of a wrapped payload into the `u64` words an NVKV stream is made of.
+///
+/// # Errors
+///
+/// - `EIO` if the combined length is not a whole number of words.
+/// - `ENOMEM` if the buffer cannot be allocated.
+pub(crate) fn nvkv_words(payload_0: &[u8], payload_1: &[u8]) -> Result<KVVec<u64>> {
+ let bytes = SBufferIter::new_reader([payload_0, payload_1]).flush_into_kvec(GFP_KERNEL)?;
+ let words = bytes.chunks_exact(size_of::<u64>());
+ if !words.remainder().is_empty() {
+ return Err(EIO);
+ }
+
+ let mut out = KVVec::with_capacity(bytes.len() / size_of::<u64>(), GFP_KERNEL)?;
+ for word in words {
+ let word: [u8; size_of::<u64>()] = word.try_into().map_err(|_| EIO)?;
+ out.push(u64::from_le_bytes(word), GFP_KERNEL)?;
+ }
+
+ Ok(out)
+}
+
mod encode;
pub(crate) use encode::*;
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 20/32] gpu: nova-core: vgpu: query VF assignments and properties
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (18 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 19/32] gpu: nova-core: gsp: factor out NVKV payload conversion Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 21/32] gpu: nova-core: vgpu: add instance create/destroy Zhi Wang
` (11 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
A vGPU instance is created in the VFIO open path. Before creating it,
the path queries the VF's assigned vGPU type and its properties to
determine how much of each resource to allocate.
Add GMC queries for the assigned vGPU type and its properties, decoding
the NVKV response with the vGPU properties schema.
Co-developed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp.rs | 1 +
drivers/gpu/nova-core/gsp/cmdq.rs | 1 -
drivers/gpu/nova-core/gsp/fw.rs | 2 +-
drivers/gpu/nova-core/vgpu.rs | 2 +
drivers/gpu/nova-core/vgpu/commands.rs | 71 +++++++++++++++++
drivers/gpu/nova-core/vgpu/fw.rs | 17 +++++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 93 +++++++++++++++++++++++
7 files changed, 185 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/nova-core/vgpu/commands.rs
create mode 100644 drivers/gpu/nova-core/vgpu/fw.rs
create mode 100644 drivers/gpu/nova-core/vgpu/fw/commands.rs
diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs
index 5b1e4eb7cad8..c961ea029fed 100644
--- a/drivers/gpu/nova-core/gsp.rs
+++ b/drivers/gpu/nova-core/gsp.rs
@@ -28,6 +28,7 @@
mod regs;
pub(crate) use fw::{
+ r000_00 as bindings,
GspFmcBootParams,
GspFwWprMeta,
LibosMemoryRegionInitArgument,
diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index 137242ca0b11..f4a0c8671bc8 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -505,7 +505,6 @@ pub(crate) struct GmcResponse {
/// Response status (`NV_STATUS` code). Zero means success.
pub(crate) status: u32,
/// Response payload copied out of the message queue.
- #[expect(dead_code)]
pub(crate) payload: KVec<u8>,
}
diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw.rs
index ac94fb564bfd..882780f38ba6 100644
--- a/drivers/gpu/nova-core/gsp/fw.rs
+++ b/drivers/gpu/nova-core/gsp/fw.rs
@@ -2,7 +2,7 @@
// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
pub(crate) mod commands;
-mod r000_00;
+pub(crate) mod r000_00;
// Alias to avoid repeating the version number with every use.
use r000_00 as bindings;
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 6a876f8539f0..0f9f5be752b5 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -20,6 +20,8 @@
gsp::commands::FifoEngineList, //
};
+mod commands;
+mod fw;
mod hal;
mod vram;
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
new file mode 100644
index 000000000000..b5fa3575b1d7
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! vGPU firmware command operations.
+//!
+//! Sends requests, checks responses and coordinates the firmware command
+//! sequences used by instance lifecycle operations.
+
+use kernel::prelude::*;
+
+use crate::gsp::{
+ cmdq::Cmdq,
+ nvkv::{
+ nvkv_words,
+ Decoder,
+ UnknownKeyPolicy, //
+ },
+};
+
+use super::fw::commands::VgpuPropertiesSchema;
+
+pub(super) use super::fw::commands::{
+ Dbdf,
+ VgpuProperties, //
+};
+
+use super::fw::{
+ GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE,
+ GMCAPI_CMD_QUERY_VGPU_PROPERTIES, //
+};
+
+/// Query the vGPU type assigned to a VF by its DBDF.
+#[expect(dead_code)]
+pub(super) fn query_assigned_vf_type(cmdq: &Cmdq<'_>, dbdf: Dbdf) -> Result<u32> {
+ let request = u64::from(dbdf.into_raw()).to_le_bytes();
+ let response =
+ cmdq.send_gmc_and_receive(GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE, &request, 64)?;
+ if response.status != 0 {
+ return Err(EIO);
+ }
+ let bytes = response.payload.get(..4).ok_or(ENODEV)?;
+ Ok(u32::from_le_bytes(bytes.try_into().map_err(|_| EINVAL)?))
+}
+
+/// Query and decode the firmware properties of one vGPU type.
+#[expect(dead_code)]
+pub(super) fn query_vgpu_properties(cmdq: &Cmdq<'_>, type_id: u32) -> Result<KBox<VgpuProperties>> {
+ let response = cmdq.send_gmc_and_receive(
+ GMCAPI_CMD_QUERY_VGPU_PROPERTIES,
+ &type_id.to_le_bytes(),
+ 4096,
+ )?;
+ if response.status != 0 {
+ return Err(EIO);
+ }
+
+ let properties = decode_vgpu_properties(&response.payload)?;
+ if properties.type_id != type_id || properties.max_instance == 0 {
+ return Err(EINVAL);
+ }
+ Ok(properties)
+}
+
+/// Decodes a byte-oriented GMC vGPU-properties response with the typed NVKV schema.
+fn decode_vgpu_properties(payload: &[u8]) -> Result<KBox<VgpuProperties>> {
+ let words = nvkv_words(payload, &[])?;
+ let decoder = Decoder::new(&words, UnknownKeyPolicy::Ignore);
+ let mut schema = VgpuPropertiesSchema::default();
+ let properties = KBox::try_init(decoder.decode(&mut schema)?, GFP_KERNEL)?;
+ Ok(properties)
+}
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
new file mode 100644
index 000000000000..23097cb13121
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! vGPU firmware interface.
+//!
+//! Exposes command constants and communication buffer layout types from
+//! raw firmware bindings.
+
+pub(super) mod commands;
+
+use crate::gsp::bindings;
+
+pub(super) const GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE;
+
+pub(super) const GMCAPI_CMD_QUERY_VGPU_PROPERTIES: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_QUERY_VGPU_PROPERTIES;
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
new file mode 100644
index 000000000000..51226bbca757
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! Wire types and codecs for vGPU commands.
+//!
+//! Defines request encoders and response schemas independently of command
+//! submission and instance lifecycle operations.
+
+use kernel::{
+ alloc::ArrayVec,
+ bitfield, //
+};
+
+use crate::gsp::nvkv::{
+ nvkv_decode,
+ Array,
+ Key,
+ KeyId,
+ Required, //
+};
+
+bitfield! {
+ pub(in crate::vgpu) struct Dbdf(u32) {
+ 2:0 function;
+ 7:3 device;
+ 15:8 bus;
+ 31:16 domain;
+ }
+}
+
+nvkv_decode! {
+ pub(in crate::vgpu) struct VgpuPropertiesSchema => VgpuProperties {
+ // TODO: `name`/`class` required?
+ name: Array<u8, { VgpuProperties::STRING_LEN }, { Self::TYPE_NAME_KEY }>,
+ class: Array<u8, { VgpuProperties::STRING_LEN }, { Self::CLASS_KEY }>,
+ type_id: Required<u32, { Self::TYPE_ID_KEY }>,
+ bar1_length: Required<u64, { Self::BAR1_LENGTH_KEY }>,
+ max_instance: Required<u32, { Self::MAX_INSTANCE_KEY }>,
+ ecc: Key<u32, { Self::ECC_KEY }>,
+ profile_size: Required<u64, { Self::PROFILE_SIZE_KEY }>,
+ max_fps: Key<u32, { Self::MAX_FPS_KEY }>,
+ num_heads: Key<u32, { Self::NUM_HEADS_KEY }>,
+ max_res_x: Key<u32, { Self::MAX_RES_X_KEY }>,
+ max_res_y: Key<u32, { Self::MAX_RES_Y_KEY }>,
+ dev_id: Required<u32, { Self::DEV_ID_KEY }>,
+ subsystem_id: Required<u32, { Self::SUBSYSTEM_ID_KEY }>,
+ fb_length: Required<u64, { Self::FB_LENGTH_KEY }>,
+ gsp_heap_size: Required<u64, { Self::GSP_HEAP_SIZE_KEY }>,
+ fb_reservation: Required<u64, { Self::FB_RESERVATION_KEY }>,
+ }
+}
+
+impl VgpuPropertiesSchema {
+ const TYPE_NAME_KEY: KeyId = 0x3100;
+ const CLASS_KEY: KeyId = 0x3101;
+ const TYPE_ID_KEY: KeyId = 0x3102;
+ const BAR1_LENGTH_KEY: KeyId = 0x3103;
+ const MAX_INSTANCE_KEY: KeyId = 0x3104;
+ const ECC_KEY: KeyId = 0x3105;
+ const PROFILE_SIZE_KEY: KeyId = 0x3106;
+ const MAX_FPS_KEY: KeyId = 0x3107;
+ const NUM_HEADS_KEY: KeyId = 0x3108;
+ const MAX_RES_X_KEY: KeyId = 0x3109;
+ const MAX_RES_Y_KEY: KeyId = 0x310A;
+ const DEV_ID_KEY: KeyId = 0x310B;
+ const SUBSYSTEM_ID_KEY: KeyId = 0x310C;
+ const FB_LENGTH_KEY: KeyId = 0x310D;
+ const GSP_HEAP_SIZE_KEY: KeyId = 0x310E;
+ const FB_RESERVATION_KEY: KeyId = 0x310F;
+}
+
+pub(in crate::vgpu) struct VgpuProperties {
+ name: ArrayVec<u8, { Self::STRING_LEN }>,
+ class: ArrayVec<u8, { Self::STRING_LEN }>,
+ pub(in crate::vgpu) type_id: u32,
+ pub(in crate::vgpu) bar1_length: u64,
+ pub(in crate::vgpu) max_instance: u32,
+ ecc: u32,
+ profile_size: u64,
+ max_fps: u32,
+ num_heads: u32,
+ max_res_x: u32,
+ max_res_y: u32,
+ pub(in crate::vgpu) dev_id: u32,
+ pub(in crate::vgpu) subsystem_id: u32,
+ pub(in crate::vgpu) fb_length: u64,
+ pub(in crate::vgpu) gsp_heap_size: u64,
+ fb_reservation: u64,
+}
+
+impl VgpuProperties {
+ const STRING_LEN: usize = 64;
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 21/32] gpu: nova-core: vgpu: add instance create/destroy
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (19 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 20/32] gpu: nova-core: vgpu: query VF assignments and properties Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 22/32] gpu: nova-core: vgpu: encode vGPU boot requests Zhi Wang
` (10 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
A vGPU instance holds the resources used by a VF. The VF must have a
vGPU type assigned before instance creation. The instance lifetime is
intended to follow VFIO device use: create it on open and destroy it
on close.
Add an instance registry to VgpuManager with creation and destruction
operations. Creation reserves channel IDs and a VRAM slot according
to the assigned vGPU type; destruction releases those reservations.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 12 +-
drivers/gpu/nova-core/vgpu.rs | 23 ++-
drivers/gpu/nova-core/vgpu/commands.rs | 1 -
drivers/gpu/nova-core/vgpu/instance.rs | 225 +++++++++++++++++++++++++
4 files changed, 247 insertions(+), 14 deletions(-)
create mode 100644 drivers/gpu/nova-core/vgpu/instance.rs
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index ebf29b06a8e1..61adf412bae7 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -54,14 +54,16 @@
},
};
-#[cfg_attr(not(CONFIG_KUNIT = "y"), expect(dead_code))]
mod channel;
mod hal;
mod regs;
use self::channel::TOTAL_CHANNELS;
-pub(crate) use self::channel::ChannelIdPool;
+pub(crate) use self::channel::{
+ ChannelIdPool,
+ ChannelIdReservation, //
+};
macro_rules! define_chipset {
({ $($variant:ident = $value:expr),* $(,)* }) =>
@@ -313,7 +315,7 @@ struct GspResources<'gpu> {
#[pin_data]
pub(crate) struct Gpu<'gpu> {
spec: Spec,
- vgpu: Option<VgpuManager<'gpu>>,
+ vgpu: Option<Pin<KBox<VgpuManager<'gpu>>>>,
/// GSP event interrupt registration.
///
/// Declared before `gsp_resources` so it is dropped first: `free_irq` runs, waiting out any
@@ -444,7 +446,7 @@ pub(crate) fn new<'a>(
let info = &gsp_resources.boot_result.static_info;
match gsp_resources.vgpu_state {
VgpuState::Disabled => None,
- VgpuState::Enabled { .. } => Some(VgpuManager::new(
+ VgpuState::Enabled { .. } => Some(KBox::pin_init(VgpuManager::new(
// SAFETY: `chid_pool` is initialized above at its final pinned address.
// The private manager and its pool borrow cannot escape this `Gpu`.
// Completed field drop order drops the manager before the pool; on failure,
@@ -453,7 +455,7 @@ pub(crate) fn new<'a>(
&info.fifo_engine_list,
info.vmmu_segment_size,
TOTAL_CHANNELS,
- )),
+ ), GFP_KERNEL)?),
}
},
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 0f9f5be752b5..f3e40e6de6f0 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -4,8 +4,10 @@
use kernel::{
device,
+ new_mutex,
pci,
- prelude::*, //
+ prelude::*,
+ sync::Mutex, //
};
use crate::{
@@ -23,6 +25,7 @@
mod commands;
mod fw;
mod hal;
+mod instance;
mod vram;
/// vGPU state detected during GPU construction.
@@ -88,9 +91,13 @@ fn query_state(
}
}
+use self::instance::VgpuInstances;
+
/// Runtime resources for an enabled vGPU boot.
+#[pin_data]
pub(crate) struct VgpuManager<'gpu> {
- #[expect(dead_code)]
+ #[pin]
+ instances: Mutex<VgpuInstances<'gpu>>,
chid_pool: &'gpu ChannelIdPool,
vmmu_segment_size: u64,
total_channels: u32,
@@ -104,22 +111,22 @@ pub(crate) fn new(
fifo_engine_list: &FifoEngineList,
vmmu_segment_size: u64,
total_channels: u32,
- ) -> Self {
- Self {
+ ) -> impl PinInit<Self> + use<'gpu> {
+ let fifo_engine_list = *fifo_engine_list;
+ pin_init!(Self {
+ instances <- new_mutex!(VgpuInstances::new(), "nova-core::vgpu-instances"),
chid_pool,
vmmu_segment_size,
total_channels,
- fifo_engine_list: *fifo_engine_list,
- }
+ fifo_engine_list,
+ })
}
/// Returns the VMMU segment size in bytes, or zero if GSP-RM omitted it.
- #[expect(dead_code)]
const fn vmmu_segment_size(&self) -> u64 {
self.vmmu_segment_size
}
- #[expect(dead_code)]
const fn total_channels(&self) -> u32 {
self.total_channels
}
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
index b5fa3575b1d7..bdedd7fc21ad 100644
--- a/drivers/gpu/nova-core/vgpu/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -43,7 +43,6 @@ pub(super) fn query_assigned_vf_type(cmdq: &Cmdq<'_>, dbdf: Dbdf) -> Result<u32>
}
/// Query and decode the firmware properties of one vGPU type.
-#[expect(dead_code)]
pub(super) fn query_vgpu_properties(cmdq: &Cmdq<'_>, type_id: u32) -> Result<KBox<VgpuProperties>> {
let response = cmdq.send_gmc_and_receive(
GMCAPI_CMD_QUERY_VGPU_PROPERTIES,
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
new file mode 100644
index 000000000000..99a8f47e72d1
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+use core::num::NonZeroUsize;
+
+use kernel::{
+ prelude::*,
+ ptr::Alignment,
+ sizes::SizeConstants, //
+};
+
+use crate::gsp::cmdq::Cmdq;
+
+use crate::{
+ gpu::ChannelIdReservation,
+ mm::GpuMm, //
+};
+
+use super::{
+ vram::{
+ VgpuVramLayout,
+ VgpuVramSlot,
+ VgpuVramSlotAllocator, //
+ },
+ VgpuManager, //
+};
+
+use super::commands::{
+ query_vgpu_properties,
+ Dbdf,
+ VgpuProperties, //
+};
+
+/// Guest Function ID. GFID 0 is reserved for the PF; VFs start at 1.
+#[repr(transparent)]
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub(super) struct Gfid(pub(super) u32);
+
+/// Resource requirements and device identity for one vGPU type.
+#[expect(dead_code)]
+pub(super) struct VgpuType {
+ vgpu_type_id: u32,
+ bar1_length: u64,
+ max_instance: u32,
+ pci_dev_id: u32,
+ pci_subsys_id: u32,
+ fb_length: u64,
+ gsp_heap_size: u64,
+}
+
+impl VgpuType {
+ fn from_properties(properties: &VgpuProperties) -> Self {
+ Self {
+ vgpu_type_id: properties.type_id,
+ bar1_length: properties.bar1_length,
+ max_instance: properties.max_instance,
+ pci_dev_id: properties.dev_id,
+ pci_subsys_id: properties.subsystem_id,
+ fb_length: properties.fb_length,
+ gsp_heap_size: properties.gsp_heap_size,
+ }
+ }
+}
+
+/// A vGPU instance and the resources reserved for it.
+#[expect(dead_code)]
+pub(super) struct VgpuInstance<'gpu> {
+ pub(super) gfid: Gfid,
+ dbdf: Dbdf,
+ vgpu_type: VgpuType,
+ vm_pid: u32,
+ chids: ChannelIdReservation<'gpu>,
+ vram_slot: VgpuVramSlot,
+}
+
+/// Identity and firmware profile used to allocate an instance.
+pub(super) struct InstanceInfo {
+ gfid: Gfid,
+ dbdf: Dbdf,
+ vgpu_type: VgpuType,
+ vm_pid: u32,
+}
+
+#[expect(dead_code)]
+impl InstanceInfo {
+ pub(super) const fn new(gfid: Gfid, dbdf: Dbdf, vgpu_type: VgpuType, vm_pid: u32) -> Self {
+ Self {
+ gfid,
+ dbdf,
+ vgpu_type,
+ vm_pid,
+ }
+ }
+}
+
+/// Registry of live vGPU instances.
+pub(super) struct VgpuInstances<'gpu> {
+ instances: KVec<VgpuInstance<'gpu>>,
+ vram_slots: Option<VgpuVramSlotAllocator>,
+}
+
+#[expect(dead_code)]
+impl<'gpu> VgpuInstances<'gpu> {
+ pub(super) const fn new() -> Self {
+ Self {
+ instances: KVec::new(),
+ vram_slots: None,
+ }
+ }
+
+ fn alloc_vram_slot(&mut self, mm: &GpuMm<'_>, layout: VgpuVramLayout) -> Result<VgpuVramSlot> {
+ let replace_empty_pool = match self.vram_slots.as_ref() {
+ Some(allocator) if allocator.is_empty() => !allocator.matches_layout(layout)?,
+ _ => false,
+ };
+ if replace_empty_pool {
+ self.vram_slots = None;
+ }
+
+ if let Some(allocator) = self.vram_slots.as_mut() {
+ return allocator.alloc(layout);
+ }
+
+ let mut allocator = VgpuVramSlotAllocator::new(mm, layout)?;
+ let slot = allocator.alloc(layout)?;
+ self.vram_slots = Some(allocator);
+ Ok(slot)
+ }
+
+ fn release_vram_slot(&mut self, slot: VgpuVramSlot) -> Result {
+ self.vram_slots.as_mut().ok_or(EIO)?.release(slot);
+ Ok(())
+ }
+
+ /// Allocate resources and register a new inactive vGPU instance.
+ pub(super) fn allocate_instance(
+ &mut self,
+ mm: &GpuMm<'_>,
+ vgpu: &VgpuManager<'gpu>,
+ info: InstanceInfo,
+ ) -> Result<Gfid> {
+ let InstanceInfo {
+ gfid,
+ dbdf,
+ vgpu_type,
+ vm_pid,
+ } = info;
+
+ if self
+ .instances
+ .iter()
+ .any(|instance| instance.gfid == gfid || instance.dbdf == dbdf)
+ {
+ return Err(EEXIST);
+ }
+ let profile_instances = self
+ .instances
+ .iter()
+ .filter(|instance| instance.vgpu_type.vgpu_type_id == vgpu_type.vgpu_type_id)
+ .count();
+ if vgpu_type.max_instance == 0
+ || profile_instances
+ >= usize::try_from(vgpu_type.max_instance).map_err(|_| EOVERFLOW)?
+ {
+ return Err(ENOSPC);
+ }
+ // Reserve registry capacity before acquiring resources so publishing
+ // the completed instance cannot fail due to memory pressure.
+ self.instances.reserve(1, GFP_KERNEL)?;
+
+ let num_chid = vgpu
+ .total_channels()
+ .checked_div(vgpu_type.max_instance)
+ .filter(|count| *count != 0)
+ .ok_or(EINVAL)?;
+ let chids = vgpu.chid_pool.reserve_ids(
+ NonZeroUsize::new(usize::try_from(num_chid).map_err(|_| EOVERFLOW)?).ok_or(EINVAL)?,
+ Alignment::SZ_1,
+ )?;
+ let layout = VgpuVramLayout {
+ type_id: vgpu_type.vgpu_type_id,
+ max_slots: vgpu_type.max_instance,
+ fb_size: vgpu_type.fb_length,
+ heap_size: vgpu_type.gsp_heap_size,
+ fb_align: vgpu.vmmu_segment_size(),
+ };
+ let vram_slot = self.alloc_vram_slot(mm, layout)?;
+
+ let instance = VgpuInstance {
+ gfid,
+ dbdf,
+ vgpu_type,
+ vm_pid,
+ chids,
+ vram_slot,
+ };
+ match self.instances.push_within_capacity(instance) {
+ Ok(()) => Ok(gfid),
+ Err(error) => {
+ let VgpuInstance { vram_slot, .. } = error.0;
+ self.release_vram_slot(vram_slot)?;
+ Err(EIO)
+ }
+ }
+ }
+
+ /// Remove an instance and release its channel and VRAM reservations.
+ pub(super) fn destroy_instance(&mut self, gfid: Gfid) -> Result {
+ let index = self
+ .instances
+ .iter()
+ .position(|instance| instance.gfid == gfid)
+ .ok_or(ENOENT)?;
+ let instance = self.instances.remove(index).map_err(|_| EIO)?;
+ let VgpuInstance { vram_slot, .. } = instance;
+ self.release_vram_slot(vram_slot)
+ }
+}
+
+/// Query and decode one vGPU type using the typed NVKV schema.
+#[expect(dead_code)]
+pub(super) fn query_vgpu_type(cmdq: &Cmdq<'_>, type_id: u32) -> Result<VgpuType> {
+ let properties = query_vgpu_properties(cmdq, type_id)?;
+ Ok(VgpuType::from_properties(&properties))
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 22/32] gpu: nova-core: vgpu: encode vGPU boot requests
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (20 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 21/32] gpu: nova-core: vgpu: add instance create/destroy Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 23/32] gpu: nova-core: vgpu: add GSP plugin communication buffers Zhi Wang
` (9 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The vGPU boot command describes a vGPU's channel assignment, framebuffer,
plugin heap and log buffers to GSP. During vGPU instance creation,
once all resources have been allocated, this command registers them
with GSP-RM and boots the GSP plugin.
Add the NVKV request schema and encoder, including the channel map
and guest framebuffer segment arrays.
Co-developed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/nvkv.rs | 11 ++
drivers/gpu/nova-core/gsp/nvkv/encode.rs | 12 ++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 163 +++++++++++++++++++++-
3 files changed, 185 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/gsp/nvkv.rs b/drivers/gpu/nova-core/gsp/nvkv.rs
index 9f2119b98b26..8d8dd4435354 100644
--- a/drivers/gpu/nova-core/gsp/nvkv.rs
+++ b/drivers/gpu/nova-core/gsp/nvkv.rs
@@ -168,6 +168,17 @@ pub(crate) struct Array<T: Default + Copy, const N: usize, const KEY_ID: KeyId>
vec: ArrayVec<T, N>,
}
+impl<T: Default + Copy, const N: usize, const KEY_ID: KeyId> Array<T, N, KEY_ID> {
+ /// Creates an array filled from `values`.
+ ///
+ /// Fails with `EINVAL` if `values` is longer than `N`.
+ pub(crate) fn new(values: &[T]) -> Result<Self> {
+ let mut vec = ArrayVec::default();
+ vec.extend_from_slice(values)?;
+ Ok(Self { vec })
+ }
+}
+
bitfield! {
/// The op word that starts each NVKV operation.
struct Op(u64) {
diff --git a/drivers/gpu/nova-core/gsp/nvkv/encode.rs b/drivers/gpu/nova-core/gsp/nvkv/encode.rs
index 0047be65e8a9..1f4df24d8c9c 100644
--- a/drivers/gpu/nova-core/gsp/nvkv/encode.rs
+++ b/drivers/gpu/nova-core/gsp/nvkv/encode.rs
@@ -6,6 +6,7 @@
use kernel::prelude::*;
use super::{
+ Array,
EncodedStream,
Index,
Key,
@@ -145,6 +146,17 @@ fn encode(&self, encoder: &mut Encoder) -> Result {
}
}
+impl<T, const N: usize, const KEY_ID: KeyId> Encodable for Array<T, N, KEY_ID>
+where
+ T: Default + Copy,
+ for<'a> IndexedKey<&'a [T], KEY_ID>: Encodable,
+{
+ #[inline(always)]
+ fn encode(&self, encoder: &mut Encoder) -> Result {
+ IndexedKey::<&[T], KEY_ID>::new(Index::new::<0>(), self.vec.as_slice()).encode(encoder)
+ }
+}
+
impl<T: Encodable> Encodable for Option<T> {
#[inline(always)]
fn encode(&self, encoder: &mut Encoder) -> Result {
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
index 51226bbca757..3af84c584dd6 100644
--- a/drivers/gpu/nova-core/vgpu/fw/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -8,12 +8,18 @@
use kernel::{
alloc::ArrayVec,
- bitfield, //
+ bitfield,
+ prelude::*, //
};
use crate::gsp::nvkv::{
nvkv_decode,
+ nvkv_encode,
Array,
+ Encodable,
+ EncodedStream,
+ Encoder,
+ Index,
Key,
KeyId,
Required, //
@@ -28,6 +34,161 @@ pub(in crate::vgpu) struct Dbdf(u32) {
}
}
+#[derive(Clone, Copy)]
+struct SwizzId(u32);
+
+impl SwizzId {
+ const WHOLE_GPU: Self = Self(0xFFFF_FFFF);
+}
+
+impl From<SwizzId> for u32 {
+ fn from(value: SwizzId) -> Self {
+ value.0
+ }
+}
+
+bitfield! {
+ pub(in crate::vgpu) struct ChannelMapEntry(u64) {
+ 15:0 engine_type;
+ 31:16 index;
+ 63:32 chid_offset;
+ }
+}
+
+impl ChannelMapEntry {
+ const KEY: KeyId = 0x1001;
+
+ #[expect(dead_code)]
+ pub(in crate::vgpu) fn new(engine_type: usize, index: u32, chid_offset: u32) -> Result<Self> {
+ Self::zeroed()
+ .try_with_engine_type(u64::try_from(engine_type).map_err(|_| EOVERFLOW)?)
+ .and_then(|entry| entry.try_with_index(u64::from(index)))
+ .and_then(|entry| entry.try_with_chid_offset(u64::from(chid_offset)))
+ }
+}
+
+impl Encodable for KVVec<ChannelMapEntry> {
+ fn encode(&self, encoder: &mut Encoder) -> Result {
+ // SAFETY: `ChannelMapEntry` is a `bitfield!` over `u64`, i.e.
+ // `#[repr(transparent)]` around a `u64`, so the entries are
+ // layout-compatible with `u64` and can be viewed as a `u64` slice.
+ let slice = unsafe { core::slice::from_raw_parts(self.as_ptr().cast::<u64>(), self.len()) };
+ encoder.encode_array64(ChannelMapEntry::KEY, Index::new::<0>(), slice)
+ }
+}
+
+bitfield! {
+ struct VgpuBootloadOptions(u64) {
+ }
+}
+
+nvkv_encode! {
+ struct VgpuBootloadRequest {
+ dbdf: Key<Dbdf, { Self::DBDF_KEY }, u32>,
+ gfid: Key<u32, { Self::GFID_KEY }>,
+ vgpu_type: Key<u32, { Self::VGPU_TYPE_KEY }>,
+ vm_pid: Key<u32, { Self::VM_PID_KEY }>,
+ swizz_id: Key<SwizzId, { Self::SWIZZ_ID_KEY }, u32>,
+ num_channels: Key<u32, { Self::NUM_CHANNELS_KEY }>,
+ num_plugin_channels: Key<u32, { Self::NUM_PLUGIN_CHANNELS_KEY }>,
+ guest_fb_segment_count: Key<u32, { Self::GUEST_FB_SEGMENT_COUNT_KEY }>,
+ options: Key<VgpuBootloadOptions, { Self::OPTIONS_KEY }, u64>,
+ channel_mapping: KVVec<ChannelMapEntry>,
+ guest_fb_segment_phys_addr: Array<u64, 8, { Self::GUEST_FB_SEGMENT_PHYS_ADDR_KEY }>,
+ guest_fb_segment_length: Array<u64, 8, { Self::GUEST_FB_SEGMENT_LENGTH_KEY }>,
+ plugin_heap_phys_addr: Key<u64, { Self::PLUGIN_HEAP_PHYS_ADDR_KEY }>,
+ plugin_heap_length: Key<u64, { Self::PLUGIN_HEAP_LENGTH_KEY }>,
+ ctrl_buff_offset: Key<u64, { Self::CTRL_BUFF_OFFSET_KEY }>,
+ init_task_log_offset: Key<u64, { Self::INIT_TASK_LOG_OFFSET_KEY }>,
+ init_task_log_size: Key<u64, { Self::INIT_TASK_LOG_SIZE_KEY }>,
+ vgpu_task_log_offset: Key<u64, { Self::VGPU_TASK_LOG_OFFSET_KEY }>,
+ vgpu_task_log_size: Key<u64, { Self::VGPU_TASK_LOG_SIZE_KEY }>,
+ kernel_log_offset: Key<u64, { Self::KERNEL_LOG_OFFSET_KEY }>,
+ kernel_log_size: Key<u64, { Self::KERNEL_LOG_SIZE_KEY }>,
+ mig_rm_heap_phys_addr: Key<u64, { Self::MIG_RM_HEAP_PHYS_ADDR_KEY }>,
+ mig_rm_heap_length: Key<u64, { Self::MIG_RM_HEAP_LENGTH_KEY }>,
+ }
+}
+
+impl VgpuBootloadRequest {
+ const DBDF_KEY: KeyId = 0x0001;
+ const GFID_KEY: KeyId = 0x0002;
+ const VGPU_TYPE_KEY: KeyId = 0x0003;
+ const VM_PID_KEY: KeyId = 0x0004;
+ const SWIZZ_ID_KEY: KeyId = 0x0005;
+ const NUM_CHANNELS_KEY: KeyId = 0x0006;
+ const NUM_PLUGIN_CHANNELS_KEY: KeyId = 0x0007;
+ const GUEST_FB_SEGMENT_COUNT_KEY: KeyId = 0x0008;
+ const OPTIONS_KEY: KeyId = 0x1000;
+ const GUEST_FB_SEGMENT_PHYS_ADDR_KEY: KeyId = 0x1002;
+ const GUEST_FB_SEGMENT_LENGTH_KEY: KeyId = 0x1003;
+ const PLUGIN_HEAP_PHYS_ADDR_KEY: KeyId = 0x1004;
+ const PLUGIN_HEAP_LENGTH_KEY: KeyId = 0x1005;
+ const CTRL_BUFF_OFFSET_KEY: KeyId = 0x1006;
+ const INIT_TASK_LOG_OFFSET_KEY: KeyId = 0x1007;
+ const INIT_TASK_LOG_SIZE_KEY: KeyId = 0x1008;
+ const VGPU_TASK_LOG_OFFSET_KEY: KeyId = 0x1009;
+ const VGPU_TASK_LOG_SIZE_KEY: KeyId = 0x100A;
+ const KERNEL_LOG_OFFSET_KEY: KeyId = 0x100B;
+ const KERNEL_LOG_SIZE_KEY: KeyId = 0x100C;
+ const MIG_RM_HEAP_PHYS_ADDR_KEY: KeyId = 0x100D;
+ const MIG_RM_HEAP_LENGTH_KEY: KeyId = 0x100E;
+}
+
+/// Encodes a `VGPU_BOOTLOAD` request using the typed NVKV schema.
+#[expect(dead_code)]
+#[expect(clippy::too_many_arguments)]
+pub(in crate::vgpu) fn encode_vgpu_bootload(
+ dbdf: Dbdf,
+ gfid: u32,
+ vgpu_type: u32,
+ vm_pid: u32,
+ num_channels: u32,
+ num_plugin_channels: u32,
+ channel_mapping: KVVec<ChannelMapEntry>,
+ guest_fb_address: u64,
+ guest_fb_length: u64,
+ plugin_heap_address: u64,
+ plugin_heap_length: u64,
+ ctrl_buffer_offset: u64,
+ init_log_address: u64,
+ init_log_size: u64,
+ vgpu_log_address: u64,
+ vgpu_log_size: u64,
+ kernel_log_address: u64,
+ kernel_log_size: u64,
+) -> Result<EncodedStream> {
+ let request = VgpuBootloadRequest {
+ dbdf: dbdf.into(),
+ gfid: gfid.into(),
+ vgpu_type: vgpu_type.into(),
+ vm_pid: vm_pid.into(),
+ swizz_id: SwizzId::WHOLE_GPU.into(),
+ num_channels: num_channels.into(),
+ num_plugin_channels: num_plugin_channels.into(),
+ guest_fb_segment_count: 1.into(),
+ options: VgpuBootloadOptions::zeroed().into(),
+ channel_mapping,
+ guest_fb_segment_phys_addr: Array::new(&[guest_fb_address])?,
+ guest_fb_segment_length: Array::new(&[guest_fb_length])?,
+ plugin_heap_phys_addr: plugin_heap_address.into(),
+ plugin_heap_length: plugin_heap_length.into(),
+ ctrl_buff_offset: ctrl_buffer_offset.into(),
+ init_task_log_offset: init_log_address.into(),
+ init_task_log_size: init_log_size.into(),
+ vgpu_task_log_offset: vgpu_log_address.into(),
+ vgpu_task_log_size: vgpu_log_size.into(),
+ kernel_log_offset: kernel_log_address.into(),
+ kernel_log_size: kernel_log_size.into(),
+ mig_rm_heap_phys_addr: 0.into(),
+ mig_rm_heap_length: 0.into(),
+ };
+
+ let mut encoder = Encoder::new();
+ request.encode(&mut encoder)?;
+ Ok(encoder.finish())
+}
+
nvkv_decode! {
pub(in crate::vgpu) struct VgpuPropertiesSchema => VgpuProperties {
// TODO: `name`/`class` required?
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 23/32] gpu: nova-core: vgpu: add GSP plugin communication buffers
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (21 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 22/32] gpu: nova-core: vgpu: encode vGPU boot requests Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:48 ` [PATCH v2 24/32] gpu: nova-core: vgpu: add instance boot and shutdown Zhi Wang
` (8 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The GSP plugin uses a communication region in its management heap for
control data and logs. The vGPU manager reads its boot-ready marker through
BAR1.
Map this region with BarMapping and expose the firmware-defined control
and log regions. Keep the mapping's BarUser borrow until explicit teardown.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/mm.rs | 1 -
drivers/gpu/nova-core/vgpu.rs | 1 +
drivers/gpu/nova-core/vgpu/fw.rs | 15 ++
drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 204 ++++++++++++++++++
4 files changed, 220 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs
index 016d99608aeb..d1cad5ad52fc 100644
--- a/drivers/gpu/nova-core/mm.rs
+++ b/drivers/gpu/nova-core/mm.rs
@@ -67,7 +67,6 @@ macro_rules! impl_pfn_bounded {
mod regs;
pub(super) mod tlb;
pub(super) mod vmm;
-#[expect(dead_code)]
pub(crate) mod vram;
/// GPU Memory Manager - owns all core MM components.
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index f3e40e6de6f0..8919322dc057 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -24,6 +24,7 @@
mod commands;
mod fw;
+mod gsp_plugin_comm;
mod hal;
mod instance;
mod vram;
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
index 23097cb13121..aabe114b55c2 100644
--- a/drivers/gpu/nova-core/vgpu/fw.rs
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -10,6 +10,21 @@
use crate::gsp::bindings;
+pub(super) use bindings::{
+ GSP_PLUGIN_BOOTLOADED,
+ VGPU_CPU_GSP_COMMUNICATION_BUFF_TOTAL_SIZE,
+ VGPU_CPU_GSP_CTRL_BUFF_REGION as RawControlRegion,
+ VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_INIT_TASK_LOG_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE, //
+};
+
pub(super) const GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE: u32 =
bindings::GMCAPI_COMMANDS_GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE;
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
new file mode 100644
index 000000000000..d2139309b6be
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! GSP plugin communication buffer mappings and access.
+
+use kernel::prelude::*;
+
+use crate::mm::{
+ bar_user::{
+ BarMapping,
+ BarUser, //
+ },
+ vram::VramRegion,
+ GpuMm, //
+};
+
+use super::fw::{
+ self,
+ RawControlRegion, //
+};
+
+/// Physical VRAM regions containing the vGPU plugin logs.
+pub(super) struct PluginLogRegions {
+ init: VramRegion,
+ vgpu: VramRegion,
+ kernel: VramRegion,
+}
+
+#[expect(dead_code)]
+impl PluginLogRegions {
+ pub(super) const fn init(&self) -> &VramRegion {
+ &self.init
+ }
+
+ pub(super) const fn vgpu(&self) -> &VramRegion {
+ &self.vgpu
+ }
+
+ pub(super) const fn kernel(&self) -> &VramRegion {
+ &self.kernel
+ }
+}
+
+fn take_region(region: &VramRegion, cursor: &mut u64, size: u32) -> Result<VramRegion> {
+ let end = cursor.checked_add(u64::from(size)).ok_or(EOVERFLOW)?;
+ let subregion = region.subregion(*cursor..end)?;
+ *cursor = end;
+ Ok(subregion)
+}
+
+/// BAR1 mapping of the plugin communication region in its management heap.
+///
+/// r000 layout, with byte offsets from the management heap (not to scale):
+///
+/// ```text
+/// 0x000000 +----------------------------------------+
+/// | Control (boot-ready marker) 4 KiB |
+/// 0x001000 +----------------------------------------+
+/// | Response 4 KiB |
+/// 0x002000 +----------------------------------------+
+/// | Message 4 KiB |
+/// 0x003000 +----------------------------------------+
+/// | Migration 2 MiB |
+/// 0x203000 +----------------------------------------+
+/// | Error 4 KiB |
+/// 0x204000 +----------------------------------------+
+/// | Init task log 128 KiB |
+/// 0x224000 +----------------------------------------+
+/// | vGPU task log 256 KiB |
+/// 0x264000 +----------------------------------------+
+/// | Kernel task log 64 KiB |
+/// 0x274000 +----------------------------------------+
+/// | Guest RPC trace 64 KiB |
+/// 0x284000 +----------------------------------------+
+/// ```
+pub(super) struct CommBufferRegion<'map, 'gpu> {
+ map: BarMapping<'map, 'gpu>,
+ control: VramRegion,
+ init_log: VramRegion,
+ vgpu_log: VramRegion,
+ kernel_log: VramRegion,
+}
+
+#[expect(dead_code)]
+impl<'map, 'gpu> CommBufferRegion<'map, 'gpu> {
+ /// Map the communication portion of a plugin management heap.
+ pub(super) fn new(
+ bar_user: &'map BarUser<'gpu>,
+ mm: &mut GpuMm<'_>,
+ management_heap: &VramRegion,
+ ) -> Result<Self> {
+ let total_size = u64::from(fw::VGPU_CPU_GSP_COMMUNICATION_BUFF_TOTAL_SIZE);
+ let region = management_heap.subregion(0..total_size)?;
+ let mut cursor = 0;
+
+ let control = take_region(®ion, &mut cursor, fw::VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE)?;
+ take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE,
+ )?;
+ take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE,
+ )?;
+ take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE,
+ )?;
+ take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE,
+ )?;
+ let init_log = take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_INIT_TASK_LOG_BUFF_REGION_SIZE,
+ )?;
+ let vgpu_log = take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE,
+ )?;
+ let kernel_log = take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE,
+ )?;
+ take_region(
+ ®ion,
+ &mut cursor,
+ fw::VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE,
+ )?;
+
+ if cursor != total_size || control.size() != u64::try_from(size_of::<RawControlRegion>())? {
+ return Err(EINVAL);
+ }
+
+ let map = BarMapping::new(bar_user, mm, region, true)?;
+
+ Ok(Self {
+ map,
+ control,
+ init_log,
+ vgpu_log,
+ kernel_log,
+ })
+ }
+
+ fn region_offset(&self, region: &VramRegion) -> Result<usize> {
+ let offset = region
+ .address()
+ .checked_sub(self.map.region().address())
+ .ok_or(EINVAL)?;
+ if offset.checked_add(region.size()).ok_or(EOVERFLOW)? > self.map.region().size() {
+ return Err(EINVAL);
+ }
+
+ usize::try_from(offset).map_err(|_| EOVERFLOW)
+ }
+
+ fn io_offset(&self, region: &VramRegion, field: usize, width: usize) -> Result<usize> {
+ let field_end = field.checked_add(width).ok_or(EOVERFLOW)?;
+ if u64::try_from(field_end).map_err(|_| EOVERFLOW)? > region.size() {
+ return Err(EINVAL);
+ }
+
+ self.region_offset(region)?
+ .checked_add(field)
+ .ok_or(EOVERFLOW)
+ }
+
+ fn read_u32(&self, region: &VramRegion, field: usize) -> Result<u32> {
+ self.map
+ .try_read32(self.io_offset(region, field, size_of::<u32>())?)
+ }
+
+ /// Return the physical regions occupied by the three plugin logs.
+ pub(super) fn plugin_logs(&self) -> PluginLogRegions {
+ PluginLogRegions {
+ init: self.init_log.clone(),
+ vgpu: self.vgpu_log.clone(),
+ kernel: self.kernel_log.clone(),
+ }
+ }
+
+ /// Return whether firmware has published the plugin boot marker.
+ pub(super) fn is_plugin_ready(&self) -> Result<bool> {
+ let value = self.read_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_seq_num),
+ )?;
+
+ Ok(value == fw::GSP_PLUGIN_BOOTLOADED)
+ }
+
+ /// Invalidate the PTEs and release the communication mapping.
+ pub(super) fn destroy(self, mm: &mut GpuMm<'_>) -> Result {
+ self.map.destroy(mm)
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 24/32] gpu: nova-core: vgpu: add instance boot and shutdown
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (22 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 23/32] gpu: nova-core: vgpu: add GSP plugin communication buffers Zhi Wang
@ 2026-09-14 7:48 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 25/32] gpu: nova-core: vgpu: initialize GSP plugin RPC buffers Zhi Wang
` (7 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:48 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
Once a vGPU instance has been allocated, the boot command registers all
its resources with the GSP-RM and GSP plugin, and starts the plugin. During
vGPU shutdown, SHUTDOWN stops the plugin before the instance's resources
are released.
Start the GSP plugin with the instance's channel map, framebuffer,
management heap and log regions. Clear a reused slot's ready marker
before boot and wait for the plugin to publish a new one.
Wait for SHUTDOWN completion and CLEANUP before unmapping the communication
buffer and returning the channel and VRAM reservations.
Co-developed-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Alok Kumar <alkumar@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp/cmdq.rs | 2 -
drivers/gpu/nova-core/gsp/commands.rs | 1 -
drivers/gpu/nova-core/vgpu/commands.rs | 80 +++++++-
drivers/gpu/nova-core/vgpu/fw.rs | 12 ++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 2 -
drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 15 +-
drivers/gpu/nova-core/vgpu/instance.rs | 194 +++++++++++++++++-
7 files changed, 287 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/cmdq.rs
index f4a0c8671bc8..62b97a43fefd 100644
--- a/drivers/gpu/nova-core/gsp/cmdq.rs
+++ b/drivers/gpu/nova-core/gsp/cmdq.rs
@@ -734,7 +734,6 @@ pub(crate) fn send_gmc_and_receive_timeout(
}
/// Sends a synchronous GMC command and checks its status-only reply.
- #[expect(dead_code)]
pub(crate) fn send_gmc_and_check_status(&self, command_id: u32, payload: &[u8]) -> Result {
let response = self.send_gmc_and_receive(command_id, payload, 0)?;
if response.status == 0 {
@@ -753,7 +752,6 @@ pub(crate) fn send_gmc_and_check_status(&self, command_id: u32, payload: &[u8])
///
/// Both callbacks run with the queue locked and must not reenter this queue or reset it.
/// Their second argument is the raw `max_resp_or_status` word of the event header.
- #[expect(dead_code)]
pub(crate) fn send_gmc_and_wait_event(
&self,
command_id: u32,
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 7945a191bd08..769ff6aea748 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -60,7 +60,6 @@ pub(crate) struct FifoEngineList {
}
impl FifoEngineList {
- #[expect(dead_code)]
pub(crate) fn gmc_ids(&self) -> &[u32] {
// PANIC: The type invariant bounds `count` by the array capacity.
&self.gmc_ids[..self.count]
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
index bdedd7fc21ad..a2df36b901a8 100644
--- a/drivers/gpu/nova-core/vgpu/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -6,7 +6,12 @@
//! Sends requests, checks responses and coordinates the firmware command
//! sequences used by instance lifecycle operations.
-use kernel::prelude::*;
+use kernel::{
+ device,
+ prelude::*,
+ time::Delta,
+ transmute::AsBytes, //
+};
use crate::gsp::{
cmdq::Cmdq,
@@ -17,6 +22,8 @@
},
};
+use super::instance::Gfid;
+
use super::fw::commands::VgpuPropertiesSchema;
pub(super) use super::fw::commands::{
@@ -25,8 +32,12 @@
};
use super::fw::{
+ GMCAPI_CMD_BOOTLOAD_GSP_VGPU_PLUGIN_TASK,
+ GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES,
GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE,
- GMCAPI_CMD_QUERY_VGPU_PROPERTIES, //
+ GMCAPI_CMD_QUERY_VGPU_PROPERTIES,
+ GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK,
+ GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_COMPLETE, //
};
/// Query the vGPU type assigned to a VF by its DBDF.
@@ -68,3 +79,68 @@ fn decode_vgpu_properties(payload: &[u8]) -> Result<KBox<VgpuProperties>> {
let properties = KBox::try_init(decoder.decode(&mut schema)?, GFP_KERNEL)?;
Ok(properties)
}
+
+/// Send BOOTLOAD and check its firmware status.
+pub(super) fn send_bootload(cmdq: &Cmdq<'_>, payload: &[u64]) -> Result {
+ let response = cmdq.send_gmc_and_receive_timeout(
+ GMCAPI_CMD_BOOTLOAD_GSP_VGPU_PLUGIN_TASK,
+ AsBytes::as_bytes(payload),
+ 0,
+ Delta::from_secs(10),
+ )?;
+ if response.status != 0 {
+ return Err(EIO);
+ }
+ Ok(())
+}
+
+/// Shut down a vGPU plugin task and wait for its completion event.
+pub(super) fn send_shutdown(
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+) -> Result {
+ let payload = gfid.0.to_le_bytes();
+
+ cmdq.send_gmc_and_wait_event(
+ GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK,
+ &payload,
+ Delta::from_secs(10),
+ |command_id, _max_response_size, _sequence, payload_0, payload_1| {
+ if command_id != GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_COMPLETE
+ || !payload
+ .iter()
+ .copied()
+ .eq(Iterator::chain(payload_0.iter(), payload_1.iter())
+ .take(payload.len())
+ .copied())
+ {
+ return Ok(false);
+ }
+ Ok(true)
+ },
+ |command_id, _max_response_size, _sequence, _payload_0, _payload_1| {
+ dev_dbg!(
+ dev,
+ "shutdown: ignoring unrelated event command={:#x}\n",
+ command_id,
+ );
+ Ok(())
+ },
+ )?;
+ Ok(())
+}
+
+/// Release firmware resources after a plugin task has stopped.
+pub(super) fn send_cleanup(
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+) -> Result {
+ cmdq.send_gmc_and_check_status(
+ GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES,
+ &gfid.0.to_le_bytes(),
+ )?;
+ dev_dbg!(dev, "cleanup: gfid={} done\n", gfid.0);
+ Ok(())
+}
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
index aabe114b55c2..1528cc56ce74 100644
--- a/drivers/gpu/nova-core/vgpu/fw.rs
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -30,3 +30,15 @@
pub(super) const GMCAPI_CMD_QUERY_VGPU_PROPERTIES: u32 =
bindings::GMCAPI_COMMANDS_GMCAPI_CMD_QUERY_VGPU_PROPERTIES;
+
+pub(super) const GMCAPI_CMD_BOOTLOAD_GSP_VGPU_PLUGIN_TASK: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_BOOTLOAD_GSP_VGPU_PLUGIN_TASK;
+
+pub(super) const GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK;
+
+pub(super) const GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_COMPLETE: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_COMPLETE;
+
+pub(super) const GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES;
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
index 3af84c584dd6..2e6518e2460b 100644
--- a/drivers/gpu/nova-core/vgpu/fw/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -58,7 +58,6 @@ pub(in crate::vgpu) struct ChannelMapEntry(u64) {
impl ChannelMapEntry {
const KEY: KeyId = 0x1001;
- #[expect(dead_code)]
pub(in crate::vgpu) fn new(engine_type: usize, index: u32, chid_offset: u32) -> Result<Self> {
Self::zeroed()
.try_with_engine_type(u64::try_from(engine_type).map_err(|_| EOVERFLOW)?)
@@ -136,7 +135,6 @@ impl VgpuBootloadRequest {
}
/// Encodes a `VGPU_BOOTLOAD` request using the typed NVKV schema.
-#[expect(dead_code)]
#[expect(clippy::too_many_arguments)]
pub(in crate::vgpu) fn encode_vgpu_bootload(
dbdf: Dbdf,
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
index d2139309b6be..af7a396021bc 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
@@ -26,7 +26,6 @@ pub(super) struct PluginLogRegions {
kernel: VramRegion,
}
-#[expect(dead_code)]
impl PluginLogRegions {
pub(super) const fn init(&self) -> &VramRegion {
&self.init
@@ -81,7 +80,6 @@ pub(super) struct CommBufferRegion<'map, 'gpu> {
kernel_log: VramRegion,
}
-#[expect(dead_code)]
impl<'map, 'gpu> CommBufferRegion<'map, 'gpu> {
/// Map the communication portion of a plugin management heap.
pub(super) fn new(
@@ -187,6 +185,19 @@ pub(super) fn plugin_logs(&self) -> PluginLogRegions {
}
}
+ /// Clear a previous boot marker before starting the plugin.
+ pub(super) fn clear_plugin_ready(&self) -> Result {
+ let offset = self.io_offset(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_seq_num),
+ size_of::<u32>(),
+ )?;
+ self.map.try_write32(0, offset)?;
+ // Complete the posted clear before firmware can publish its new marker.
+ self.map.try_read32(offset)?;
+ Ok(())
+ }
+
/// Return whether firmware has published the plugin boot marker.
pub(super) fn is_plugin_ready(&self) -> Result<bool> {
let value = self.read_u32(
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index 99a8f47e72d1..535e5ab7c2ad 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -4,19 +4,33 @@
use core::num::NonZeroUsize;
use kernel::{
+ device,
prelude::*,
ptr::Alignment,
sizes::SizeConstants, //
+ time::{
+ delay::fsleep,
+ Delta,
+ Instant,
+ Monotonic, //
+ },
};
-use crate::gsp::cmdq::Cmdq;
+use crate::gsp::{
+ cmdq::Cmdq,
+ commands::FifoEngineList, //
+};
use crate::{
gpu::ChannelIdReservation,
- mm::GpuMm, //
+ mm::{
+ bar_user::BarUser,
+ GpuMm, //
+ },
};
use super::{
+ gsp_plugin_comm::CommBufferRegion,
vram::{
VgpuVramLayout,
VgpuVramSlot,
@@ -27,10 +41,56 @@
use super::commands::{
query_vgpu_properties,
+ send_bootload,
+ send_cleanup,
+ send_shutdown,
Dbdf,
VgpuProperties, //
};
+use super::fw::commands::{
+ encode_vgpu_bootload,
+ ChannelMapEntry, //
+};
+
+/// Ready limit used by `vmiopd_negotiate_cpu_gsp_version()` for the same marker.
+const PLUGIN_READY_TIMEOUT: Delta = Delta::from_secs(10);
+
+/// Build the typed channel mapping from the GSP FIFO engine list.
+fn channel_mapping(
+ fifo_engine_list: &FifoEngineList,
+ chid_offset: u32,
+) -> Result<KVVec<ChannelMapEntry>> {
+ let mut mapping = KVVec::new();
+ for &gmc_id in fifo_engine_list.gmc_ids() {
+ let engine_type = (gmc_id & 0xffff) as usize;
+ let index = gmc_id >> 16;
+ mapping.push(
+ ChannelMapEntry::new(engine_type, index, chid_offset)?,
+ GFP_KERNEL,
+ )?;
+ }
+ Ok(mapping)
+}
+
+fn wait_plugin_ready(
+ dev: &device::Device<device::Bound>,
+ comm: &CommBufferRegion<'_, '_>,
+) -> Result {
+ let start = Instant::<Monotonic>::now();
+
+ loop {
+ if comm.is_plugin_ready()? {
+ dev_dbg!(dev, "vGPU plugin ready after {:?}\n", start.elapsed());
+ return Ok(());
+ }
+ if start.elapsed() >= PLUGIN_READY_TIMEOUT {
+ return Err(ETIMEDOUT);
+ }
+ fsleep(Delta::from_millis(1));
+ }
+}
+
/// Guest Function ID. GFID 0 is reserved for the PF; VFs start at 1.
#[repr(transparent)]
#[derive(Clone, Copy, PartialEq, Eq)]
@@ -49,6 +109,10 @@ pub(super) struct VgpuType {
}
impl VgpuType {
+ pub(super) const fn vgpu_type_id(&self) -> u32 {
+ self.vgpu_type_id
+ }
+
fn from_properties(properties: &VgpuProperties) -> Self {
Self {
vgpu_type_id: properties.type_id,
@@ -63,14 +127,79 @@ fn from_properties(properties: &VgpuProperties) -> Self {
}
/// A vGPU instance and the resources reserved for it.
-#[expect(dead_code)]
pub(super) struct VgpuInstance<'gpu> {
pub(super) gfid: Gfid,
dbdf: Dbdf,
vgpu_type: VgpuType,
vm_pid: u32,
chids: ChannelIdReservation<'gpu>,
+ num_plugin_channels: u32,
vram_slot: VgpuVramSlot,
+ comm: CommBufferRegion<'gpu, 'gpu>,
+ needs_teardown: bool,
+}
+
+impl VgpuInstance<'_> {
+ /// Bootload the GSP vGPU plugin and wait for its BAR1 ready indication.
+ fn bootload(
+ &mut self,
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ fifo_engine_list: &FifoEngineList,
+ ) -> Result {
+ let fb = &self.vram_slot.fbmem;
+ let mgmt = &self.vram_slot.mgmt_heap;
+ let logs = self.comm.plugin_logs();
+
+ let payload = encode_vgpu_bootload(
+ self.dbdf,
+ self.gfid.0,
+ self.vgpu_type.vgpu_type_id(),
+ self.vm_pid,
+ u32::try_from(self.chids.len()).map_err(|_| EOVERFLOW)?,
+ self.num_plugin_channels,
+ channel_mapping(
+ fifo_engine_list,
+ u32::try_from(self.chids.start).map_err(|_| EOVERFLOW)?,
+ )?,
+ fb.address(),
+ fb.size(),
+ mgmt.address(),
+ mgmt.size(),
+ 0,
+ logs.init().address(),
+ logs.init().size(),
+ logs.vgpu().address(),
+ logs.vgpu().size(),
+ logs.kernel().address(),
+ logs.kernel().size(),
+ )?;
+
+ dev_dbg!(
+ dev,
+ "bootload: gfid={} sending {} typed NVKV bytes\n",
+ self.gfid.0,
+ payload.len() * size_of::<u64>(),
+ );
+
+ self.comm.clear_plugin_ready()?;
+ self.needs_teardown = true;
+ send_bootload(cmdq, &payload)?;
+
+ wait_plugin_ready(dev, &self.comm)?;
+
+ dev_dbg!(dev, "bootload: gfid={} plugin ready\n", self.gfid.0);
+ Ok(())
+ }
+
+ /// Stop the plugin when firmware may own instance resources.
+ fn shutdown(&mut self, dev: &device::Device<device::Bound>, cmdq: &Cmdq<'_>) -> Result {
+ if self.needs_teardown {
+ send_shutdown(dev, cmdq, self.gfid)?;
+ dev_dbg!(dev, "shutdown: gfid={} stopped\n", self.gfid.0);
+ }
+ Ok(())
+ }
}
/// Identity and firmware profile used to allocate an instance.
@@ -132,10 +261,20 @@ fn release_vram_slot(&mut self, slot: VgpuVramSlot) -> Result {
Ok(())
}
+ fn release_instance(&mut self, instance: VgpuInstance<'gpu>, mm: &mut GpuMm<'_>) -> Result {
+ let VgpuInstance {
+ comm, vram_slot, ..
+ } = instance;
+ let result = comm.destroy(mm);
+ self.release_vram_slot(vram_slot)?;
+ result
+ }
+
/// Allocate resources and register a new inactive vGPU instance.
pub(super) fn allocate_instance(
&mut self,
- mm: &GpuMm<'_>,
+ bar_user: &'gpu BarUser<'gpu>,
+ mm: &mut GpuMm<'_>,
vgpu: &VgpuManager<'gpu>,
info: InstanceInfo,
) -> Result<Gfid> {
@@ -185,6 +324,13 @@ pub(super) fn allocate_instance(
fb_align: vgpu.vmmu_segment_size(),
};
let vram_slot = self.alloc_vram_slot(mm, layout)?;
+ let comm = match CommBufferRegion::new(bar_user, mm, &vram_slot.mgmt_heap) {
+ Ok(comm) => comm,
+ Err(error) => {
+ self.release_vram_slot(vram_slot)?;
+ return Err(error);
+ }
+ };
let instance = VgpuInstance {
gfid,
@@ -192,28 +338,56 @@ pub(super) fn allocate_instance(
vgpu_type,
vm_pid,
chids,
+ num_plugin_channels: 3,
vram_slot,
+ comm,
+ needs_teardown: false,
};
match self.instances.push_within_capacity(instance) {
Ok(()) => Ok(gfid),
Err(error) => {
- let VgpuInstance { vram_slot, .. } = error.0;
- self.release_vram_slot(vram_slot)?;
+ self.release_instance(error.0, mm)?;
Err(EIO)
}
}
}
- /// Remove an instance and release its channel and VRAM reservations.
- pub(super) fn destroy_instance(&mut self, gfid: Gfid) -> Result {
+ /// Bootload the GSP plugin for a registered instance.
+ pub(super) fn activate_instance(
+ &mut self,
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+ fifo_engine_list: &FifoEngineList,
+ ) -> Result {
+ let instance = self
+ .instances
+ .iter_mut()
+ .find(|instance| instance.gfid == gfid)
+ .ok_or(ENOENT)?;
+ instance.bootload(dev, cmdq, fifo_engine_list)
+ }
+
+ /// Stop the plugin and release the instance's firmware and host resources.
+ pub(super) fn destroy_instance(
+ &mut self,
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ mm: &mut GpuMm<'_>,
+ gfid: Gfid,
+ ) -> Result {
let index = self
.instances
.iter()
.position(|instance| instance.gfid == gfid)
.ok_or(ENOENT)?;
+ let instance = &mut self.instances[index];
+ instance.shutdown(dev, cmdq)?;
+ if instance.needs_teardown {
+ send_cleanup(dev, cmdq, gfid)?;
+ }
let instance = self.instances.remove(index).map_err(|_| EIO)?;
- let VgpuInstance { vram_slot, .. } = instance;
- self.release_vram_slot(vram_slot)
+ self.release_instance(instance, mm)
}
}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 25/32] gpu: nova-core: vgpu: initialize GSP plugin RPC buffers
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (23 preceding siblings ...)
2026-09-14 7:48 ` [PATCH v2 24/32] gpu: nova-core: vgpu: add instance boot and shutdown Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 26/32] gpu: nova-core: vgpu: add GSP plugin RPC transactions Zhi Wang
` (6 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
After the GSP plugin has been successfully booted, the vGPU manager
uses the GSP plugin RPC interface to communicate with it through a shared
RPC buffer.
The shared buffer needs region offsets, a protocol version and initial
control and response state before the first request. The control
sequence field also carries the boot-ready marker, so initialization
must follow the plugin's ready indication.
Add BAR1 accessors to initialize the shared control and response buffers.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/mm/bar_user.rs | 10 ++
drivers/gpu/nova-core/vgpu/fw.rs | 2 +
drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 142 +++++++++++++++++-
3 files changed, 147 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs
index ef357fd516b7..b7b4bf14b56d 100644
--- a/drivers/gpu/nova-core/mm/bar_user.rs
+++ b/drivers/gpu/nova-core/mm/bar_user.rs
@@ -141,6 +141,11 @@ pub(crate) fn try_read32(&self, offset: usize) -> Result<u32> {
self.bar_user.bar1.try_read32(off)
}
+ fn try_write8(&self, value: u8, offset: usize) -> Result {
+ let off = self.bar_offset(offset)?;
+ self.bar_user.bar1.try_write8(value, off)
+ }
+
/// Write a 32-bit value at the given offset.
pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result {
let off = self.bar_offset(offset)?;
@@ -261,6 +266,11 @@ pub(crate) fn try_read32(&self, offset: usize) -> Result<u32> {
.try_read32(self.access_offset(offset, size_of::<u32>())?)
}
+ pub(crate) fn try_write8(&self, value: u8, offset: usize) -> Result {
+ self.access
+ .try_write8(value, self.access_offset(offset, size_of::<u8>())?)
+ }
+
pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result {
self.access
.try_write32(value, self.access_offset(offset, size_of::<u32>())?)
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
index 1528cc56ce74..03225b9833c3 100644
--- a/drivers/gpu/nova-core/vgpu/fw.rs
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -15,12 +15,14 @@
VGPU_CPU_GSP_COMMUNICATION_BUFF_TOTAL_SIZE,
VGPU_CPU_GSP_CTRL_BUFF_REGION as RawControlRegion,
VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_CTRL_BUFF_VERSION,
VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE,
VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE,
VGPU_CPU_GSP_INIT_TASK_LOG_BUFF_REGION_SIZE,
VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE,
VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE,
VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE,
+ VGPU_CPU_GSP_RESPONSE_BUFF_REGION as RawResponseRegion,
VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE,
VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE, //
};
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
index af7a396021bc..5d129a1b908f 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
@@ -16,7 +16,8 @@
use super::fw::{
self,
- RawControlRegion, //
+ RawControlRegion,
+ RawResponseRegion, //
};
/// Physical VRAM regions containing the vGPU plugin logs.
@@ -75,9 +76,14 @@ fn take_region(region: &VramRegion, cursor: &mut u64, size: u32) -> Result<VramR
pub(super) struct CommBufferRegion<'map, 'gpu> {
map: BarMapping<'map, 'gpu>,
control: VramRegion,
+ response: VramRegion,
+ message: VramRegion,
+ migration: VramRegion,
+ error: VramRegion,
init_log: VramRegion,
vgpu_log: VramRegion,
kernel_log: VramRegion,
+ guest_trace: VramRegion,
}
impl<'map, 'gpu> CommBufferRegion<'map, 'gpu> {
@@ -92,22 +98,22 @@ pub(super) fn new(
let mut cursor = 0;
let control = take_region(®ion, &mut cursor, fw::VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE)?;
- take_region(
+ let response = take_region(
®ion,
&mut cursor,
fw::VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE,
)?;
- take_region(
+ let message = take_region(
®ion,
&mut cursor,
fw::VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE,
)?;
- take_region(
+ let migration = take_region(
®ion,
&mut cursor,
fw::VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE,
)?;
- take_region(
+ let error = take_region(
®ion,
&mut cursor,
fw::VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE,
@@ -127,13 +133,16 @@ pub(super) fn new(
&mut cursor,
fw::VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE,
)?;
- take_region(
+ let guest_trace = take_region(
®ion,
&mut cursor,
fw::VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE,
)?;
- if cursor != total_size || control.size() != u64::try_from(size_of::<RawControlRegion>())? {
+ if cursor != total_size
+ || control.size() != u64::try_from(size_of::<RawControlRegion>())?
+ || response.size() != u64::try_from(size_of::<RawResponseRegion>())?
+ {
return Err(EINVAL);
}
@@ -142,9 +151,14 @@ pub(super) fn new(
Ok(Self {
map,
control,
+ response,
+ message,
+ migration,
+ error,
init_log,
vgpu_log,
kernel_log,
+ guest_trace,
})
}
@@ -176,6 +190,21 @@ fn read_u32(&self, region: &VramRegion, field: usize) -> Result<u32> {
.try_read32(self.io_offset(region, field, size_of::<u32>())?)
}
+ fn write_u8(&self, region: &VramRegion, field: usize, value: u8) -> Result {
+ self.map
+ .try_write8(value, self.io_offset(region, field, size_of::<u8>())?)
+ }
+
+ fn write_u32(&self, region: &VramRegion, field: usize, value: u32) -> Result {
+ self.map
+ .try_write32(value, self.io_offset(region, field, size_of::<u32>())?)
+ }
+
+ fn write_u64(&self, region: &VramRegion, field: usize, value: u64) -> Result {
+ self.map
+ .try_write64(value, self.io_offset(region, field, size_of::<u64>())?)
+ }
+
/// Return the physical regions occupied by the three plugin logs.
pub(super) fn plugin_logs(&self) -> PluginLogRegions {
PluginLogRegions {
@@ -208,6 +237,105 @@ pub(super) fn is_plugin_ready(&self) -> Result<bool> {
Ok(value == fw::GSP_PLUGIN_BOOTLOADED)
}
+ /// Initialize the shared control and response buffers for plugin RPC.
+ #[expect(dead_code)]
+ pub(super) fn initialize(&self) -> Result {
+ self.write_u64(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.response_buff_offset),
+ u64::try_from(self.region_offset(&self.response)?)?,
+ )?;
+ self.write_u64(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_buff_offset),
+ u64::try_from(self.region_offset(&self.message)?)?,
+ )?;
+ self.write_u64(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.migration_buff_offset),
+ u64::try_from(self.region_offset(&self.migration)?)?,
+ )?;
+ self.write_u64(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.error_buff_offset),
+ u64::try_from(self.region_offset(&self.error)?)?,
+ )?;
+ self.write_u64(
+ &self.control,
+ core::mem::offset_of!(
+ RawControlRegion,
+ __bindgen_anon_1.guest_rpc_trace_buff_offset
+ ),
+ u64::try_from(self.region_offset(&self.guest_trace)?)?,
+ )?;
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(
+ RawControlRegion,
+ __bindgen_anon_1.migration_buf_cpu_access_offset
+ ),
+ 0,
+ )?;
+ self.write_u8(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.is_migration_in_progress),
+ 0,
+ )?;
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.error_buff_cpu_get_idx),
+ 0,
+ )?;
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(
+ RawControlRegion,
+ __bindgen_anon_1.guest_rpc_trace_buff_cpu_get_idx
+ ),
+ 0,
+ )?;
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.attached_vgpu_count),
+ 1,
+ )?;
+ self.write_u8(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.is_gr_init_done),
+ 0,
+ )?;
+
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_type),
+ 0,
+ )?;
+ // Replace the boot-ready marker with the initial RPC sequence.
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_seq_num),
+ 0,
+ )?;
+ self.write_u32(
+ &self.response,
+ core::mem::offset_of!(
+ RawResponseRegion,
+ __bindgen_anon_1.message_seq_num_processed
+ ),
+ 0,
+ )?;
+ self.write_u32(
+ &self.response,
+ core::mem::offset_of!(RawResponseRegion, __bindgen_anon_1.result_code),
+ 0,
+ )?;
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.version),
+ fw::VGPU_CPU_GSP_CTRL_BUFF_VERSION,
+ )
+ }
+
/// Invalidate the PTEs and release the communication mapping.
pub(super) fn destroy(self, mm: &mut GpuMm<'_>) -> Result {
self.map.destroy(mm)
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 26/32] gpu: nova-core: vgpu: add GSP plugin RPC transactions
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (24 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 25/32] gpu: nova-core: vgpu: initialize GSP plugin RPC buffers Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 27/32] gpu: nova-core: vgpu: negotiate the GSP plugin RPC version Zhi Wang
` (5 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The GSP plugin processes requests after the vGPU manager rings its VF
doorbell and publishes completion in the shared response buffer.
Add PluginRpc to own the communication mapping and track request
sequences. Copy each payload before publishing its sequence, ring the
doorbell and wait for the matching completion, checking firmware status
and enforcing a timeout.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/regs.rs | 33 +++-
drivers/gpu/nova-core/vgpu.rs | 1 +
drivers/gpu/nova-core/vgpu/fw.rs | 11 ++
drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 49 +++++-
drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs | 150 ++++++++++++++++++
drivers/gpu/nova-core/vgpu/instance.rs | 17 +-
6 files changed, 251 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index bf43c71a53ee..af953aedb87b 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -7,13 +7,17 @@
Io,
Mmio, //
},
+ prelude::*,
sizes::SizeConstants,
time, //
};
use pin_init::Zeroable;
use crate::{
- driver::NovaRegisters,
+ driver::{
+ Bar0,
+ NovaRegisters, //
+ },
falcon::{
DmaTrfCmdSize,
FalconCoreRev,
@@ -39,6 +43,33 @@
pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {}
}
+// VIRTUAL_FUNCTION
+
+register! {
+ base: NovaRegisters;
+
+ // PF BAR0 exposes the virtual-function register window at 0x00b8_0000.
+ pub(crate) NV_VIRTUAL_FUNCTION_PRIV_DOORBELL(u32) @ 0x00b8_2200 {
+ 31:0 handle;
+ }
+}
+
+impl NV_VIRTUAL_FUNCTION_PRIV_DOORBELL {
+ const DOORBELL_STRIDE: u32 = 32;
+ const DOORBELL_VECTOR: u32 = 17;
+
+ /// Notify the GSP plugin for the given guest function and read back the doorbell.
+ pub(crate) fn ring_gsp_plugin(bar0: Bar0<'_>, gfid: u32) -> Result {
+ let value = gfid
+ .checked_mul(Self::DOORBELL_STRIDE)
+ .and_then(|value| value.checked_add(Self::DOORBELL_VECTOR))
+ .ok_or(EOVERFLOW)?;
+ bar0.try_write_reg(Self::zeroed().with_handle(value))?;
+ bar0.try_read(NV_VIRTUAL_FUNCTION_PRIV_DOORBELL)?;
+ Ok(())
+ }
+}
+
// PGC6 register space.
//
// `GC6` is a GPU low-power state where VRAM is in self-refresh and the GPU is powered down (except
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 8919322dc057..221a2804f5da 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -25,6 +25,7 @@
mod commands;
mod fw;
mod gsp_plugin_comm;
+mod gsp_plugin_rpc;
mod hal;
mod instance;
mod vram;
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
index 03225b9833c3..9925d5ccf71f 100644
--- a/drivers/gpu/nova-core/vgpu/fw.rs
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -44,3 +44,14 @@
pub(super) const GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES: u32 =
bindings::GMCAPI_COMMANDS_GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES;
+
+/// State observed in the response buffer for an expected RPC sequence.
+pub(super) enum RpcResponse {
+ Pending {
+ /// Last sequence completed by firmware.
+ sequence: u32,
+ },
+ Complete {
+ status: u32,
+ },
+}
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
index 5d129a1b908f..20695929a58c 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
@@ -17,7 +17,8 @@
use super::fw::{
self,
RawControlRegion,
- RawResponseRegion, //
+ RawResponseRegion,
+ RpcResponse, //
};
/// Physical VRAM regions containing the vGPU plugin logs.
@@ -238,7 +239,6 @@ pub(super) fn is_plugin_ready(&self) -> Result<bool> {
}
/// Initialize the shared control and response buffers for plugin RPC.
- #[expect(dead_code)]
pub(super) fn initialize(&self) -> Result {
self.write_u64(
&self.control,
@@ -336,6 +336,51 @@ pub(super) fn initialize(&self) -> Result {
)
}
+ /// Copy and publish one RPC request to firmware.
+ pub(super) fn submit(&self, message: u32, sequence: u32, data: &[u8]) -> Result {
+ if u64::try_from(data.len()).map_err(|_| EOVERFLOW)? > self.message.size() {
+ return Err(E2BIG);
+ }
+
+ for (index, chunk) in data.chunks(size_of::<u32>()).enumerate() {
+ let mut bytes = [0u8; size_of::<u32>()];
+ bytes[..chunk.len()].copy_from_slice(chunk);
+ let field = index.checked_mul(size_of::<u32>()).ok_or(EOVERFLOW)?;
+ self.write_u32(&self.message, field, u32::from_le_bytes(bytes))?;
+ }
+
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_type),
+ message,
+ )?;
+ self.write_u32(
+ &self.control,
+ core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_seq_num),
+ sequence,
+ )
+ }
+
+ /// Read firmware's response for an expected RPC sequence.
+ pub(super) fn response(&self, expected_sequence: u32) -> Result<RpcResponse> {
+ let sequence = self.read_u32(
+ &self.response,
+ core::mem::offset_of!(
+ RawResponseRegion,
+ __bindgen_anon_1.message_seq_num_processed
+ ),
+ )?;
+ if sequence != expected_sequence {
+ return Ok(RpcResponse::Pending { sequence });
+ }
+
+ let status = self.read_u32(
+ &self.response,
+ core::mem::offset_of!(RawResponseRegion, __bindgen_anon_1.result_code),
+ )?;
+ Ok(RpcResponse::Complete { status })
+ }
+
/// Invalidate the PTEs and release the communication mapping.
pub(super) fn destroy(self, mm: &mut GpuMm<'_>) -> Result {
self.map.destroy(mm)
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
new file mode 100644
index 000000000000..bc5d576d8601
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! GSP plugin RPC.
+//!
+//! ```text
+//! Host (PluginRpc) Shared RPC buffer (VRAM) GSP plugin
+//! | | |
+//! |-- BAR1: payload --------->| Message |
+//! |-- BAR1: type, sequence -->| Control |
+//! | | |
+//! |-- BAR0: VF doorbell ----------------------------->|
+//! | |<-- read request ------|
+//! | | | process RPC
+//! | |<-- completion --------|
+//! |-- poll processed seq ---->| Response |
+//! |<-- matching seq, status --| |
+//! ```
+
+use kernel::{
+ device,
+ prelude::*,
+ time::{
+ delay::fsleep,
+ Delta,
+ Instant,
+ Monotonic, //
+ },
+};
+
+use crate::{
+ driver::Bar0,
+ mm::GpuMm,
+ regs::NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, //
+};
+
+use super::{
+ fw::RpcResponse,
+ gsp_plugin_comm::CommBufferRegion,
+ instance::Gfid, //
+};
+
+/// BAR1-backed channel used to communicate with one GSP plugin.
+pub(super) struct PluginRpc<'map, 'gpu> {
+ comm: CommBufferRegion<'map, 'gpu>,
+ message_sequence: u32,
+}
+
+impl<'map, 'gpu> PluginRpc<'map, 'gpu> {
+ pub(super) fn new(comm: CommBufferRegion<'map, 'gpu>) -> Self {
+ Self {
+ comm,
+ message_sequence: 0,
+ }
+ }
+
+ pub(super) fn comm(&self) -> &CommBufferRegion<'map, 'gpu> {
+ &self.comm
+ }
+
+ /// Initialize the control and response buffers for the first RPC.
+ #[expect(dead_code)]
+ pub(super) fn init_rpc(&mut self) -> Result {
+ self.comm.initialize()?;
+ self.message_sequence = 0;
+ Ok(())
+ }
+
+ fn next_sequence(&self) -> u32 {
+ let sequence = self.message_sequence.wrapping_add(1);
+ if sequence == 0 {
+ 1
+ } else {
+ sequence
+ }
+ }
+
+ /// Write one RPC message, ring the VF doorbell, and wait for its response.
+ #[expect(dead_code)]
+ pub(super) fn rpc_call(
+ &mut self,
+ dev: &device::Device<device::Bound>,
+ bar0: Bar0<'_>,
+ gfid: Gfid,
+ message_type: u32,
+ data: &[u8],
+ ) -> Result {
+ let sequence = self.next_sequence();
+ self.comm.submit(message_type, sequence, data)?;
+ self.message_sequence = sequence;
+
+ dev_dbg!(
+ dev,
+ "vGPU RPC: gfid={} type={} bytes={} sequence={}\n",
+ gfid.0,
+ message_type,
+ data.len(),
+ sequence,
+ );
+
+ NV_VIRTUAL_FUNCTION_PRIV_DOORBELL::ring_gsp_plugin(bar0, gfid.0)?;
+ self.wait_response(dev, sequence)
+ }
+
+ fn wait_response(&self, dev: &device::Device<device::Bound>, expected_sequence: u32) -> Result {
+ let start = Instant::<Monotonic>::now();
+ let timeout = Delta::from_secs(120);
+
+ loop {
+ match self.comm.response(expected_sequence)? {
+ RpcResponse::Complete { status } => {
+ if status != 0 {
+ dev_dbg!(
+ dev,
+ "vGPU RPC: sequence {} failed with status {}\n",
+ expected_sequence,
+ status,
+ );
+ return Err(EIO);
+ }
+
+ dev_dbg!(
+ dev,
+ "vGPU RPC: sequence {} completed after {:?}\n",
+ expected_sequence,
+ start.elapsed(),
+ );
+ return Ok(());
+ }
+ RpcResponse::Pending { sequence } => {
+ if start.elapsed() >= timeout {
+ dev_dbg!(
+ dev,
+ "vGPU RPC: sequence {} timed out; last response was {}\n",
+ expected_sequence,
+ sequence,
+ );
+ return Err(ETIMEDOUT);
+ }
+ }
+ }
+ fsleep(Delta::from_millis(1));
+ }
+ }
+
+ /// Release the BAR1 mapping.
+ pub(super) fn destroy(self, mm: &mut GpuMm<'_>) -> Result {
+ self.comm.destroy(mm)
+ }
+}
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index 535e5ab7c2ad..994b046802c1 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -31,6 +31,7 @@
use super::{
gsp_plugin_comm::CommBufferRegion,
+ gsp_plugin_rpc::PluginRpc,
vram::{
VgpuVramLayout,
VgpuVramSlot,
@@ -135,7 +136,7 @@ pub(super) struct VgpuInstance<'gpu> {
chids: ChannelIdReservation<'gpu>,
num_plugin_channels: u32,
vram_slot: VgpuVramSlot,
- comm: CommBufferRegion<'gpu, 'gpu>,
+ pub(super) plugin_rpc: PluginRpc<'gpu, 'gpu>,
needs_teardown: bool,
}
@@ -149,7 +150,7 @@ fn bootload(
) -> Result {
let fb = &self.vram_slot.fbmem;
let mgmt = &self.vram_slot.mgmt_heap;
- let logs = self.comm.plugin_logs();
+ let logs = self.plugin_rpc.comm().plugin_logs();
let payload = encode_vgpu_bootload(
self.dbdf,
@@ -182,11 +183,11 @@ fn bootload(
payload.len() * size_of::<u64>(),
);
- self.comm.clear_plugin_ready()?;
+ self.plugin_rpc.comm().clear_plugin_ready()?;
self.needs_teardown = true;
send_bootload(cmdq, &payload)?;
- wait_plugin_ready(dev, &self.comm)?;
+ wait_plugin_ready(dev, self.plugin_rpc.comm())?;
dev_dbg!(dev, "bootload: gfid={} plugin ready\n", self.gfid.0);
Ok(())
@@ -263,9 +264,11 @@ fn release_vram_slot(&mut self, slot: VgpuVramSlot) -> Result {
fn release_instance(&mut self, instance: VgpuInstance<'gpu>, mm: &mut GpuMm<'_>) -> Result {
let VgpuInstance {
- comm, vram_slot, ..
+ plugin_rpc,
+ vram_slot,
+ ..
} = instance;
- let result = comm.destroy(mm);
+ let result = plugin_rpc.destroy(mm);
self.release_vram_slot(vram_slot)?;
result
}
@@ -340,7 +343,7 @@ pub(super) fn allocate_instance(
chids,
num_plugin_channels: 3,
vram_slot,
- comm,
+ plugin_rpc: PluginRpc::new(comm),
needs_teardown: false,
};
match self.instances.push_within_capacity(instance) {
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 27/32] gpu: nova-core: vgpu: negotiate the GSP plugin RPC version
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (25 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 26/32] gpu: nova-core: vgpu: add GSP plugin RPC transactions Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 28/32] gpu: nova-core: vgpu: send GSP plugin configuration parameters Zhi Wang
` (4 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The vGPU manager negotiates the RPC protocol with the booted GSP plugin
before sending configuration parameters.
Add the version-negotiation message ID and typed RPC submission.
Initialize the shared RPC buffers after the plugin reports ready, then
send the negotiation request.
Co-developed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/vgpu/commands.rs | 18 +++++++++++++++++-
drivers/gpu/nova-core/vgpu/fw.rs | 2 ++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 9 +++++++++
drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 5 +++--
drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs | 11 ++++++-----
drivers/gpu/nova-core/vgpu/instance.rs | 10 ++++++++--
6 files changed, 45 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
index a2df36b901a8..abc85b0365f2 100644
--- a/drivers/gpu/nova-core/vgpu/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -22,7 +22,13 @@
},
};
-use super::instance::Gfid;
+use crate::driver::Bar0;
+
+use super::{
+ fw::RpcMessage,
+ gsp_plugin_rpc::PluginRpc,
+ instance::Gfid, //
+};
use super::fw::commands::VgpuPropertiesSchema;
@@ -144,3 +150,13 @@ pub(super) fn send_cleanup(
dev_dbg!(dev, "cleanup: gfid={} done\n", gfid.0);
Ok(())
}
+
+/// Negotiate the host protocol with a bootloaded GSP plugin.
+pub(super) fn negotiate_plugin_version(
+ dev: &device::Device<device::Bound>,
+ bar0: Bar0<'_>,
+ gfid: Gfid,
+ rpc: &mut PluginRpc<'_, '_>,
+) -> Result {
+ rpc.rpc_call(dev, bar0, gfid, RpcMessage::VersionNegotiation, &[])
+}
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
index 9925d5ccf71f..6cec92c9b505 100644
--- a/drivers/gpu/nova-core/vgpu/fw.rs
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -27,6 +27,8 @@
VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE, //
};
+pub(super) use commands::RpcMessage;
+
pub(super) const GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE: u32 =
bindings::GMCAPI_COMMANDS_GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE;
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
index 2e6518e2460b..b765d30a1d61 100644
--- a/drivers/gpu/nova-core/vgpu/fw/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -25,6 +25,15 @@
Required, //
};
+use super::bindings;
+
+/// Message types supported by the nova-core plugin RPC channel.
+#[derive(Clone, Copy)]
+#[repr(u32)]
+pub(in crate::vgpu) enum RpcMessage {
+ VersionNegotiation = bindings::MESSAGE_NV_VGPU_CPU_RPC_MSG_VERSION_NEGOTIATION,
+}
+
bitfield! {
pub(in crate::vgpu) struct Dbdf(u32) {
2:0 function;
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
index 20695929a58c..e385ecff43fa 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
@@ -18,6 +18,7 @@
self,
RawControlRegion,
RawResponseRegion,
+ RpcMessage,
RpcResponse, //
};
@@ -337,7 +338,7 @@ pub(super) fn initialize(&self) -> Result {
}
/// Copy and publish one RPC request to firmware.
- pub(super) fn submit(&self, message: u32, sequence: u32, data: &[u8]) -> Result {
+ pub(super) fn submit(&self, message: RpcMessage, sequence: u32, data: &[u8]) -> Result {
if u64::try_from(data.len()).map_err(|_| EOVERFLOW)? > self.message.size() {
return Err(E2BIG);
}
@@ -352,7 +353,7 @@ pub(super) fn submit(&self, message: u32, sequence: u32, data: &[u8]) -> Result
self.write_u32(
&self.control,
core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_type),
- message,
+ message as u32,
)?;
self.write_u32(
&self.control,
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
index bc5d576d8601..ff009f241c32 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
@@ -35,7 +35,10 @@
};
use super::{
- fw::RpcResponse,
+ fw::{
+ RpcMessage,
+ RpcResponse, //
+ },
gsp_plugin_comm::CommBufferRegion,
instance::Gfid, //
};
@@ -59,7 +62,6 @@ pub(super) fn comm(&self) -> &CommBufferRegion<'map, 'gpu> {
}
/// Initialize the control and response buffers for the first RPC.
- #[expect(dead_code)]
pub(super) fn init_rpc(&mut self) -> Result {
self.comm.initialize()?;
self.message_sequence = 0;
@@ -76,13 +78,12 @@ fn next_sequence(&self) -> u32 {
}
/// Write one RPC message, ring the VF doorbell, and wait for its response.
- #[expect(dead_code)]
pub(super) fn rpc_call(
&mut self,
dev: &device::Device<device::Bound>,
bar0: Bar0<'_>,
gfid: Gfid,
- message_type: u32,
+ message_type: RpcMessage,
data: &[u8],
) -> Result {
let sequence = self.next_sequence();
@@ -93,7 +94,7 @@ pub(super) fn rpc_call(
dev,
"vGPU RPC: gfid={} type={} bytes={} sequence={}\n",
gfid.0,
- message_type,
+ message_type as u32,
data.len(),
sequence,
);
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index 994b046802c1..a65b95d11f88 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -22,6 +22,7 @@
};
use crate::{
+ driver::Bar0,
gpu::ChannelIdReservation,
mm::{
bar_user::BarUser,
@@ -41,6 +42,7 @@
};
use super::commands::{
+ negotiate_plugin_version,
query_vgpu_properties,
send_bootload,
send_cleanup,
@@ -355,11 +357,12 @@ pub(super) fn allocate_instance(
}
}
- /// Bootload the GSP plugin for a registered instance.
+ /// Boot the GSP plugin and negotiate its RPC version.
pub(super) fn activate_instance(
&mut self,
dev: &device::Device<device::Bound>,
cmdq: &Cmdq<'_>,
+ bar0: Bar0<'_>,
gfid: Gfid,
fifo_engine_list: &FifoEngineList,
) -> Result {
@@ -368,7 +371,10 @@ pub(super) fn activate_instance(
.iter_mut()
.find(|instance| instance.gfid == gfid)
.ok_or(ENOENT)?;
- instance.bootload(dev, cmdq, fifo_engine_list)
+ instance.bootload(dev, cmdq, fifo_engine_list)?;
+
+ instance.plugin_rpc.init_rpc()?;
+ negotiate_plugin_version(dev, bar0, gfid, &mut instance.plugin_rpc)
}
/// Stop the plugin and release the instance's firmware and host resources.
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 28/32] gpu: nova-core: vgpu: send GSP plugin configuration parameters
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (26 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 27/32] gpu: nova-core: vgpu: negotiate the GSP plugin RPC version Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 29/32] gpu: nova-core: vgpu: update the GSP plugin BME state Zhi Wang
` (3 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The GSP plugin needs the instance identity, channel allocation and host
parameters before it can serve guest requests.
Encode these parameters as an NVKV stream, prefix it with its word count
and send SETUP_CONFIG_PARAMS_AND_INIT after protocol negotiation.
Co-developed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/vgpu/commands.rs | 17 +++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 126 +++++++++++++++++++
drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs | 18 +++
drivers/gpu/nova-core/vgpu/instance.rs | 20 ++-
4 files changed, 179 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
index abc85b0365f2..2089c91b648e 100644
--- a/drivers/gpu/nova-core/vgpu/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -160,3 +160,20 @@ pub(super) fn negotiate_plugin_version(
) -> Result {
rpc.rpc_call(dev, bar0, gfid, RpcMessage::VersionNegotiation, &[])
}
+
+/// Send an instance's encoded configuration to the GSP plugin.
+pub(super) fn send_plugin_config(
+ dev: &device::Device<device::Bound>,
+ bar0: Bar0<'_>,
+ gfid: Gfid,
+ rpc: &mut PluginRpc<'_, '_>,
+ config: &[u64],
+) -> Result {
+ rpc.rpc_call_nvkv(
+ dev,
+ bar0,
+ gfid,
+ RpcMessage::SetupConfigParamsAndInit,
+ config,
+ )
+}
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
index b765d30a1d61..0386c8178962 100644
--- a/drivers/gpu/nova-core/vgpu/fw/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -32,6 +32,7 @@
#[repr(u32)]
pub(in crate::vgpu) enum RpcMessage {
VersionNegotiation = bindings::MESSAGE_NV_VGPU_CPU_RPC_MSG_VERSION_NEGOTIATION,
+ SetupConfigParamsAndInit = bindings::MESSAGE_NV_VGPU_CPU_RPC_MSG_SETUP_CONFIG_PARAMS_AND_INIT,
}
bitfield! {
@@ -259,3 +260,128 @@ pub(in crate::vgpu) struct VgpuProperties {
impl VgpuProperties {
const STRING_LEN: usize = 64;
}
+
+#[derive(Clone, Copy)]
+enum HypervisorType {
+ Unknown = 4,
+}
+
+impl From<HypervisorType> for u32 {
+ fn from(value: HypervisorType) -> Self {
+ value as u32
+ }
+}
+
+#[derive(Clone, Copy)]
+enum CpuArch {
+ Aarch64 = 1,
+ X86_64 = 2,
+}
+
+impl CpuArch {
+ fn host() -> Result<Self> {
+ if cfg!(target_arch = "x86_64") {
+ Ok(Self::X86_64)
+ } else if cfg!(target_arch = "aarch64") {
+ Ok(Self::Aarch64)
+ } else {
+ Err(EOPNOTSUPP)
+ }
+ }
+}
+
+impl From<CpuArch> for u32 {
+ fn from(value: CpuArch) -> Self {
+ value as u32
+ }
+}
+
+#[derive(Clone, Copy)]
+struct MigrationFeature(u32);
+
+impl MigrationFeature {
+ const PRESERVE_CTX_BUF: Self = Self(0x4000);
+}
+
+impl From<MigrationFeature> for u32 {
+ fn from(value: MigrationFeature) -> Self {
+ value.0
+ }
+}
+
+bitfield! {
+ struct FeatureFlags(u64) {
+ 3:3 enable_uvm => bool;
+ 5:5 vmm_migration => bool;
+ }
+}
+
+nvkv_encode! {
+ struct PluginConfigParamsRequest {
+ uuid: Key<[u8; 16], { Self::UUID_KEY }>,
+ dbdf: Key<Dbdf, { Self::DBDF_KEY }, u32>,
+ dev_inst: Key<u32, { Self::DEV_INST_KEY }>,
+ vgpu_type: Key<u32, { Self::VGPU_TYPE_KEY }>,
+ vm_pid: Key<u32, { Self::VM_PID_KEY }>,
+ swizz_id: Key<SwizzId, { Self::SWIZZ_ID_KEY }, u32>,
+ num_channels: Key<u32, { Self::NUM_CHANNELS_KEY }>,
+ num_plugin_channels: Key<u32, { Self::NUM_PLUGIN_CHANNELS_KEY }>,
+ vmm_cap: Key<u32, { Self::VMM_CAP_KEY }>,
+ migration_feature: Key<MigrationFeature, { Self::MIGRATION_FEATURE_KEY }, u32>,
+ hypervisor_type: Key<HypervisorType, { Self::HYPERVISOR_TYPE_KEY }, u32>,
+ cpu_arch: Key<CpuArch, { Self::CPU_ARCH_KEY }, u32>,
+ page_size: Key<u64, { Self::PAGE_SIZE_KEY }>,
+ feature_flags: Key<FeatureFlags, { Self::FEATURE_FLAGS_KEY }, u64>,
+ }
+}
+
+impl PluginConfigParamsRequest {
+ const UUID_KEY: KeyId = 0x0001;
+ const DBDF_KEY: KeyId = 0x0002;
+ const DEV_INST_KEY: KeyId = 0x0004;
+ const VGPU_TYPE_KEY: KeyId = 0x0005;
+ const VM_PID_KEY: KeyId = 0x0006;
+ const SWIZZ_ID_KEY: KeyId = 0x0010;
+ const NUM_CHANNELS_KEY: KeyId = 0x0011;
+ const NUM_PLUGIN_CHANNELS_KEY: KeyId = 0x0012;
+ const VMM_CAP_KEY: KeyId = 0x0020;
+ const MIGRATION_FEATURE_KEY: KeyId = 0x0021;
+ const HYPERVISOR_TYPE_KEY: KeyId = 0x0022;
+ const CPU_ARCH_KEY: KeyId = 0x0023;
+ const PAGE_SIZE_KEY: KeyId = 0x0024;
+ const FEATURE_FLAGS_KEY: KeyId = 0x0030;
+}
+
+/// Encodes plugin configuration parameters using the typed NVKV schema.
+pub(in crate::vgpu) fn encode_plugin_config_params(
+ uuid: [u8; 16],
+ dbdf: Dbdf,
+ vgpu_type: u32,
+ vm_pid: u32,
+ num_channels: u32,
+ num_plugin_channels: u32,
+) -> Result<EncodedStream> {
+ let request = PluginConfigParamsRequest {
+ uuid: uuid.into(),
+ dbdf: dbdf.into(),
+ dev_inst: 0.into(),
+ vgpu_type: vgpu_type.into(),
+ vm_pid: vm_pid.into(),
+ swizz_id: SwizzId::WHOLE_GPU.into(),
+ num_channels: num_channels.into(),
+ num_plugin_channels: num_plugin_channels.into(),
+ vmm_cap: 0.into(),
+ migration_feature: MigrationFeature::PRESERVE_CTX_BUF.into(),
+ hypervisor_type: HypervisorType::Unknown.into(),
+ cpu_arch: CpuArch::host()?.into(),
+ page_size: u64::try_from(kernel::page::PAGE_SIZE)?.into(),
+ feature_flags: FeatureFlags::zeroed()
+ .with_enable_uvm(false)
+ .with_vmm_migration(true)
+ .into(),
+ };
+
+ let mut encoder = Encoder::new();
+ request.encode(&mut encoder)?;
+ Ok(encoder.finish())
+}
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
index ff009f241c32..2b9bccd8acb5 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_rpc.rs
@@ -26,6 +26,7 @@
Instant,
Monotonic, //
},
+ transmute::AsBytes, //
};
use crate::{
@@ -103,6 +104,23 @@ pub(super) fn rpc_call(
self.wait_response(dev, sequence)
}
+ /// Send an NVKV stream prefixed by its word count.
+ pub(super) fn rpc_call_nvkv(
+ &mut self,
+ dev: &device::Device<device::Bound>,
+ bar0: Bar0<'_>,
+ gfid: Gfid,
+ message_type: RpcMessage,
+ encoded: &[u64],
+ ) -> Result {
+ let word_count = u64::try_from(encoded.len()).map_err(|_| EOVERFLOW)?;
+ let mut payload = KVec::new();
+ payload.extend_from_slice(&word_count.to_le_bytes(), GFP_KERNEL)?;
+ payload.extend_from_slice(AsBytes::as_bytes(encoded), GFP_KERNEL)?;
+
+ self.rpc_call(dev, bar0, gfid, message_type, &payload)
+ }
+
fn wait_response(&self, dev: &device::Device<device::Bound>, expected_sequence: u32) -> Result {
let start = Instant::<Monotonic>::now();
let timeout = Delta::from_secs(120);
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index a65b95d11f88..c3ec24f48682 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -46,12 +46,14 @@
query_vgpu_properties,
send_bootload,
send_cleanup,
+ send_plugin_config,
send_shutdown,
Dbdf,
VgpuProperties, //
};
use super::fw::commands::{
+ encode_plugin_config_params,
encode_vgpu_bootload,
ChannelMapEntry, //
};
@@ -195,6 +197,19 @@ fn bootload(
Ok(())
}
+ fn configure_plugin(&mut self, dev: &device::Device<device::Bound>, bar0: Bar0<'_>) -> Result {
+ let config = encode_plugin_config_params(
+ [0; 16],
+ self.dbdf,
+ self.vgpu_type.vgpu_type_id(),
+ self.vm_pid,
+ u32::try_from(self.chids.len()).map_err(|_| EOVERFLOW)?,
+ self.num_plugin_channels,
+ )?;
+
+ send_plugin_config(dev, bar0, self.gfid, &mut self.plugin_rpc, &config)
+ }
+
/// Stop the plugin when firmware may own instance resources.
fn shutdown(&mut self, dev: &device::Device<device::Bound>, cmdq: &Cmdq<'_>) -> Result {
if self.needs_teardown {
@@ -357,7 +372,7 @@ pub(super) fn allocate_instance(
}
}
- /// Boot the GSP plugin and negotiate its RPC version.
+ /// Boot and configure the GSP plugin for a registered instance.
pub(super) fn activate_instance(
&mut self,
dev: &device::Device<device::Bound>,
@@ -374,7 +389,8 @@ pub(super) fn activate_instance(
instance.bootload(dev, cmdq, fifo_engine_list)?;
instance.plugin_rpc.init_rpc()?;
- negotiate_plugin_version(dev, bar0, gfid, &mut instance.plugin_rpc)
+ negotiate_plugin_version(dev, bar0, gfid, &mut instance.plugin_rpc)?;
+ instance.configure_plugin(dev, bar0)
}
/// Stop the plugin and release the instance's firmware and host resources.
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 29/32] gpu: nova-core: vgpu: update the GSP plugin BME state
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (27 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 28/32] gpu: nova-core: vgpu: send GSP plugin configuration parameters Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 30/32] gpu: nova-core: vgpu: scrub guest VRAM with CeUtils Zhi Wang
` (2 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
The vGPU manager reports the enabled bus-mastering state to the GSP plugin
after its initial configuration. The guest can then use the vGPU from now
on.
Add the BME state request and NVKV encoder, and send the enabled state
after configuration succeeds.
Co-developed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/vgpu/commands.rs | 14 ++++++++++++++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 22 ++++++++++++++++++++++
drivers/gpu/nova-core/vgpu/instance.rs | 4 +++-
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
index 2089c91b648e..7bfde85ad35a 100644
--- a/drivers/gpu/nova-core/vgpu/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -37,6 +37,8 @@
VgpuProperties, //
};
+use super::fw::commands::encode_plugin_set_bme;
+
use super::fw::{
GMCAPI_CMD_BOOTLOAD_GSP_VGPU_PLUGIN_TASK,
GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES,
@@ -177,3 +179,15 @@ pub(super) fn send_plugin_config(
config,
)
}
+
+/// Update the bus-mastering state reported to the GSP plugin.
+pub(super) fn set_plugin_bme(
+ dev: &device::Device<device::Bound>,
+ bar0: Bar0<'_>,
+ gfid: Gfid,
+ rpc: &mut PluginRpc<'_, '_>,
+ enable: bool,
+) -> Result {
+ let bme = encode_plugin_set_bme(enable)?;
+ rpc.rpc_call_nvkv(dev, bar0, gfid, RpcMessage::UpdateBmeState, &bme)
+}
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
index 0386c8178962..7030479441e8 100644
--- a/drivers/gpu/nova-core/vgpu/fw/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -33,6 +33,7 @@
pub(in crate::vgpu) enum RpcMessage {
VersionNegotiation = bindings::MESSAGE_NV_VGPU_CPU_RPC_MSG_VERSION_NEGOTIATION,
SetupConfigParamsAndInit = bindings::MESSAGE_NV_VGPU_CPU_RPC_MSG_SETUP_CONFIG_PARAMS_AND_INIT,
+ UpdateBmeState = bindings::MESSAGE_NV_VGPU_CPU_RPC_MSG_UPDATE_BME_STATE,
}
bitfield! {
@@ -385,3 +386,24 @@ pub(in crate::vgpu) fn encode_plugin_config_params(
request.encode(&mut encoder)?;
Ok(encoder.finish())
}
+
+nvkv_encode! {
+ struct PluginSetBmeRequest {
+ bme_enable: Key<bool, { Self::BME_ENABLE_KEY }, u32>,
+ }
+}
+
+impl PluginSetBmeRequest {
+ const BME_ENABLE_KEY: KeyId = 0x0100;
+}
+
+/// Encodes a plugin BME state update using the typed NVKV schema.
+pub(in crate::vgpu) fn encode_plugin_set_bme(enable: bool) -> Result<EncodedStream> {
+ let request = PluginSetBmeRequest {
+ bme_enable: enable.into(),
+ };
+
+ let mut encoder = Encoder::new();
+ request.encode(&mut encoder)?;
+ Ok(encoder.finish())
+}
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index c3ec24f48682..5d71de0ad108 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -48,6 +48,7 @@
send_cleanup,
send_plugin_config,
send_shutdown,
+ set_plugin_bme,
Dbdf,
VgpuProperties, //
};
@@ -390,7 +391,8 @@ pub(super) fn activate_instance(
instance.plugin_rpc.init_rpc()?;
negotiate_plugin_version(dev, bar0, gfid, &mut instance.plugin_rpc)?;
- instance.configure_plugin(dev, bar0)
+ instance.configure_plugin(dev, bar0)?;
+ set_plugin_bme(dev, bar0, gfid, &mut instance.plugin_rpc, true)
}
/// Stop the plugin and release the instance's firmware and host resources.
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 30/32] gpu: nova-core: vgpu: scrub guest VRAM with CeUtils
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (28 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 29/32] gpu: nova-core: vgpu: update the GSP plugin BME state Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 31/32] gpu: nova-core: add build ID headers to debugfs log buffer dumps Zhi Wang
2026-09-14 7:49 ` [PATCH v2 32/32] gpu: nova-core: vgpu: export plugin log buffers via debugfs Zhi Wang
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
Guest VRAM can retain guest data when an instance is reused.
Add a per-instance Copy Engine utility, CeUtils, that asks GSP-RM to
scrub guest VRAM and verifies completion through a hardware
semaphore page.
The vGPU manager scrubs guest VRAM immediately after allocating it and
after shutting an instance down, before returning it to the allocator.
Reserve the last channel ID in each instance range for CeUtils and report
the remaining channel count to the plugin.
Keep failed initialization in the instance registry while firmware
ownership or scrub completion is uncertain.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
.../gpu/nova-core/gsp/fw/r000_00/bindings.rs | 1 +
drivers/gpu/nova-core/vgpu.rs | 1 +
drivers/gpu/nova-core/vgpu/commands.rs | 142 ++++++++++++++-
drivers/gpu/nova-core/vgpu/fw.rs | 11 ++
drivers/gpu/nova-core/vgpu/fw/commands.rs | 48 ++++++
drivers/gpu/nova-core/vgpu/instance.rs | 61 ++++++-
drivers/gpu/nova-core/vgpu/scrubber.rs | 162 ++++++++++++++++++
7 files changed, 416 insertions(+), 10 deletions(-)
create mode 100644 drivers/gpu/nova-core/vgpu/scrubber.rs
diff --git a/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs b/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
index 3cc718bb2ab8..333256ea8a04 100644
--- a/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
+++ b/drivers/gpu/nova-core/gsp/fw/r000_00/bindings.rs
@@ -851,6 +851,7 @@ fn default() -> Self {
}
}
}
+pub const NV_ADDR_FBMEM: u32 = 2;
pub const GSP_PLUGIN_BOOTLOADED: u32 = 1315261039;
pub const VGPU_CPU_GSP_CTRL_BUFF_VERSION: u32 = 2;
pub const VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE: u32 = 4096;
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 221a2804f5da..407accc05139 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -28,6 +28,7 @@
mod gsp_plugin_rpc;
mod hal;
mod instance;
+mod scrubber;
mod vram;
/// vGPU state detected during GPU construction.
diff --git a/drivers/gpu/nova-core/vgpu/commands.rs b/drivers/gpu/nova-core/vgpu/commands.rs
index 7bfde85ad35a..63b6f0e3d862 100644
--- a/drivers/gpu/nova-core/vgpu/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/commands.rs
@@ -8,6 +8,7 @@
use kernel::{
device,
+ num::casts::usize_into_u32,
prelude::*,
time::Delta,
transmute::AsBytes, //
@@ -22,7 +23,10 @@
},
};
-use crate::driver::Bar0;
+use crate::{
+ driver::Bar0,
+ mm::PAGE_SIZE, //
+};
use super::{
fw::RpcMessage,
@@ -48,6 +52,20 @@
GMCAPI_CMD_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_COMPLETE, //
};
+use super::fw::{
+ commands::{
+ AllocCeutilsRequest,
+ AllocCeutilsResponse,
+ FreeCeutilsRequest,
+ ScrubGuestFbRequest,
+ ScrubGuestFbResponse, //
+ },
+ GMCAPI_CMD_VGPU_MGR_ALLOC_GSP_CEUTILS,
+ GMCAPI_CMD_VGPU_MGR_FREE_GSP_CEUTILS,
+ GMCAPI_CMD_VGPU_MGR_SCRUB_GUEST_FB,
+ NV_ADDR_FBMEM, //
+};
+
/// Query the vGPU type assigned to a VF by its DBDF.
#[expect(dead_code)]
pub(super) fn query_assigned_vf_type(cmdq: &Cmdq<'_>, dbdf: Dbdf) -> Result<u32> {
@@ -191,3 +209,125 @@ pub(super) fn set_plugin_bme(
let bme = encode_plugin_set_bme(enable)?;
rpc.rpc_call_nvkv(dev, bar0, gfid, RpcMessage::UpdateBmeState, &bme)
}
+
+/// Whether a failed allocation may still have transferred CHID ownership to firmware.
+pub(super) enum CeUtilsAllocError {
+ /// A matching firmware response explicitly rejected the allocation.
+ NotOwned(Error),
+ /// The request may have completed despite a transport or response-validation error.
+ MayOwn(Error),
+}
+
+/// Allocate a CeUtils channel and validate its semaphore description.
+pub(super) fn alloc_ceutils(
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+ chid: u32,
+) -> core::result::Result<u64, CeUtilsAllocError> {
+ let request = AllocCeutilsRequest {
+ gfid: gfid.0.to_le(),
+ fixed_chid: chid.to_le(),
+ force_ceid: u32::MAX.to_le(),
+ swizz_id: 0,
+ };
+
+ dev_dbg!(dev, "alloc CeUtils: gfid={} chid={}\n", gfid.0, chid,);
+
+ let response = cmdq
+ .send_gmc_and_receive(
+ GMCAPI_CMD_VGPU_MGR_ALLOC_GSP_CEUTILS,
+ <AllocCeutilsRequest as IntoBytes>::as_bytes(&request),
+ usize_into_u32::<{ size_of::<AllocCeutilsResponse>() }>(),
+ )
+ .map_err(CeUtilsAllocError::MayOwn)?;
+ if response.status != 0 {
+ return Err(CeUtilsAllocError::NotOwned(EIO));
+ }
+
+ (|| {
+ let bytes = response
+ .payload
+ .get(..size_of::<AllocCeutilsResponse>())
+ .ok_or(EMSGSIZE)?;
+ let response = AllocCeutilsResponse::read_from_bytes(bytes).map_err(|_| EINVAL)?;
+ let semaphore_address = u64::from_le(response.semaphore_address);
+ let semaphore_aperture = u32::from_le(response.semaphore_aperture);
+ let page_size = u64::try_from(PAGE_SIZE).map_err(|_| EOVERFLOW)?;
+
+ if semaphore_address == 0
+ || !semaphore_address.is_multiple_of(page_size)
+ || semaphore_aperture != NV_ADDR_FBMEM
+ {
+ return Err(EINVAL);
+ }
+
+ dev_dbg!(
+ dev,
+ "alloc CeUtils: gfid={} semaphore={:#x}\n",
+ gfid.0,
+ semaphore_address,
+ );
+ Ok(semaphore_address)
+ })()
+ .map_err(CeUtilsAllocError::MayOwn)
+}
+
+/// Release a CeUtils allocation, including one whose allocation reply was lost.
+pub(super) fn free_ceutils(
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+) -> Result {
+ let request = FreeCeutilsRequest {
+ gfid: gfid.0.to_le(),
+ };
+
+ dev_dbg!(dev, "free CeUtils: gfid={}\n", gfid.0);
+ cmdq.send_gmc_and_check_status(
+ GMCAPI_CMD_VGPU_MGR_FREE_GSP_CEUTILS,
+ <FreeCeutilsRequest as IntoBytes>::as_bytes(&request),
+ )
+}
+
+/// Submit an asynchronous guest FB scrub and return its work identifier.
+pub(super) fn submit_ceutils_scrub(
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+ fb_offset: u64,
+ fb_size: u64,
+) -> Result<u32> {
+ let request = ScrubGuestFbRequest {
+ gfid: gfid.0.to_le(),
+ reserved: 0,
+ fb_offset: fb_offset.to_le(),
+ fb_size: fb_size.to_le(),
+ };
+
+ dev_dbg!(
+ dev,
+ "submit scrub: gfid={} offset={:#x} size={:#x}\n",
+ gfid.0,
+ fb_offset,
+ fb_size,
+ );
+
+ let response = cmdq.send_gmc_and_receive(
+ GMCAPI_CMD_VGPU_MGR_SCRUB_GUEST_FB,
+ <ScrubGuestFbRequest as IntoBytes>::as_bytes(&request),
+ usize_into_u32::<{ size_of::<ScrubGuestFbResponse>() }>(),
+ )?;
+ if response.status != 0 {
+ return Err(EIO);
+ }
+
+ let bytes = response
+ .payload
+ .get(..size_of::<ScrubGuestFbResponse>())
+ .ok_or(EMSGSIZE)?;
+ let response = ScrubGuestFbResponse::read_from_bytes(bytes).map_err(|_| EINVAL)?;
+ let work_id = u32::try_from(u64::from_le(response.work_id)).map_err(|_| EOVERFLOW)?;
+
+ Ok(work_id)
+}
diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs
index 6cec92c9b505..795ce4855586 100644
--- a/drivers/gpu/nova-core/vgpu/fw.rs
+++ b/drivers/gpu/nova-core/vgpu/fw.rs
@@ -27,6 +27,8 @@
VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE, //
};
+pub(super) use bindings::NV_ADDR_FBMEM;
+
pub(super) use commands::RpcMessage;
pub(super) const GMCAPI_CMD_QUERY_ASSIGNED_VF_VGPU_TYPE: u32 =
@@ -47,6 +49,15 @@
pub(super) const GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES: u32 =
bindings::GMCAPI_COMMANDS_GMCAPI_CMD_CLEANUP_GSP_VGPU_PLUGIN_RESOURCES;
+pub(super) const GMCAPI_CMD_VGPU_MGR_ALLOC_GSP_CEUTILS: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_VGPU_MGR_ALLOC_GSP_CEUTILS;
+
+pub(super) const GMCAPI_CMD_VGPU_MGR_FREE_GSP_CEUTILS: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_VGPU_MGR_FREE_GSP_CEUTILS;
+
+pub(super) const GMCAPI_CMD_VGPU_MGR_SCRUB_GUEST_FB: u32 =
+ bindings::GMCAPI_COMMANDS_GMCAPI_CMD_VGPU_MGR_SCRUB_GUEST_FB;
+
/// State observed in the response buffer for an expected RPC sequence.
pub(super) enum RpcResponse {
Pending {
diff --git a/drivers/gpu/nova-core/vgpu/fw/commands.rs b/drivers/gpu/nova-core/vgpu/fw/commands.rs
index 7030479441e8..aabbf0987daa 100644
--- a/drivers/gpu/nova-core/vgpu/fw/commands.rs
+++ b/drivers/gpu/nova-core/vgpu/fw/commands.rs
@@ -407,3 +407,51 @@ pub(in crate::vgpu) fn encode_plugin_set_bme(enable: bool) -> Result<EncodedStre
request.encode(&mut encoder)?;
Ok(encoder.finish())
}
+
+#[repr(C)]
+#[derive(IntoBytes, zerocopy_derive::Immutable)]
+pub(in crate::vgpu) struct AllocCeutilsRequest {
+ pub(in crate::vgpu) gfid: u32,
+ pub(in crate::vgpu) fixed_chid: u32,
+ pub(in crate::vgpu) force_ceid: u32,
+ pub(in crate::vgpu) swizz_id: u32,
+}
+
+static_assert!(size_of::<AllocCeutilsRequest>() == 16);
+
+#[repr(C)]
+#[derive(FromBytes)]
+pub(in crate::vgpu) struct AllocCeutilsResponse {
+ pub(in crate::vgpu) semaphore_address: u64,
+ pub(in crate::vgpu) semaphore_aperture: u32,
+ _reserved: u32,
+}
+
+static_assert!(size_of::<AllocCeutilsResponse>() == 16);
+
+#[repr(C)]
+#[derive(IntoBytes, zerocopy_derive::Immutable)]
+pub(in crate::vgpu) struct FreeCeutilsRequest {
+ pub(in crate::vgpu) gfid: u32,
+}
+
+static_assert!(size_of::<FreeCeutilsRequest>() == 4);
+
+#[repr(C)]
+#[derive(IntoBytes, zerocopy_derive::Immutable)]
+pub(in crate::vgpu) struct ScrubGuestFbRequest {
+ pub(in crate::vgpu) gfid: u32,
+ pub(in crate::vgpu) reserved: u32,
+ pub(in crate::vgpu) fb_offset: u64,
+ pub(in crate::vgpu) fb_size: u64,
+}
+
+static_assert!(size_of::<ScrubGuestFbRequest>() == 24);
+
+#[repr(C)]
+#[derive(FromBytes)]
+pub(in crate::vgpu) struct ScrubGuestFbResponse {
+ pub(in crate::vgpu) work_id: u64,
+}
+
+static_assert!(size_of::<ScrubGuestFbResponse>() == 8);
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index 5d71de0ad108..bb01d4088b5e 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -33,6 +33,7 @@
use super::{
gsp_plugin_comm::CommBufferRegion,
gsp_plugin_rpc::PluginRpc,
+ scrubber::CeUtils,
vram::{
VgpuVramLayout,
VgpuVramSlot,
@@ -42,6 +43,7 @@
};
use super::commands::{
+ free_ceutils,
negotiate_plugin_version,
query_vgpu_properties,
send_bootload,
@@ -49,6 +51,7 @@
send_plugin_config,
send_shutdown,
set_plugin_bme,
+ CeUtilsAllocError,
Dbdf,
VgpuProperties, //
};
@@ -142,6 +145,8 @@ pub(super) struct VgpuInstance<'gpu> {
num_plugin_channels: u32,
vram_slot: VgpuVramSlot,
pub(super) plugin_rpc: PluginRpc<'gpu, 'gpu>,
+ ceutils: Option<CeUtils>,
+ initialized: bool,
needs_teardown: bool,
}
@@ -204,7 +209,7 @@ fn configure_plugin(&mut self, dev: &device::Device<device::Bound>, bar0: Bar0<'
self.dbdf,
self.vgpu_type.vgpu_type_id(),
self.vm_pid,
- u32::try_from(self.chids.len()).map_err(|_| EOVERFLOW)?,
+ u32::try_from(self.chids.len().checked_sub(1).ok_or(EINVAL)?).map_err(|_| EOVERFLOW)?,
self.num_plugin_channels,
)?;
@@ -291,9 +296,11 @@ fn release_instance(&mut self, instance: VgpuInstance<'gpu>, mm: &mut GpuMm<'_>)
result
}
- /// Allocate resources and register a new inactive vGPU instance.
+ /// Allocate resources, scrub the framebuffer and register an inactive instance.
pub(super) fn allocate_instance(
&mut self,
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
bar_user: &'gpu BarUser<'gpu>,
mm: &mut GpuMm<'_>,
vgpu: &VgpuManager<'gpu>,
@@ -331,12 +338,14 @@ pub(super) fn allocate_instance(
let num_chid = vgpu
.total_channels()
.checked_div(vgpu_type.max_instance)
- .filter(|count| *count != 0)
+ .filter(|count| *count > 1)
.ok_or(EINVAL)?;
let chids = vgpu.chid_pool.reserve_ids(
NonZeroUsize::new(usize::try_from(num_chid).map_err(|_| EOVERFLOW)?).ok_or(EINVAL)?,
Alignment::SZ_1,
)?;
+ let ceutils_chid =
+ u32::try_from(chids.end.checked_sub(1).ok_or(EINVAL)?).map_err(|_| EOVERFLOW)?;
let layout = VgpuVramLayout {
type_id: vgpu_type.vgpu_type_id,
max_slots: vgpu_type.max_instance,
@@ -362,15 +371,39 @@ pub(super) fn allocate_instance(
num_plugin_channels: 3,
vram_slot,
plugin_rpc: PluginRpc::new(comm),
+ ceutils: None,
+ initialized: false,
needs_teardown: false,
};
- match self.instances.push_within_capacity(instance) {
- Ok(()) => Ok(gfid),
+ // Register ownership before firmware work so an uncertain result leaves
+ // the reservations reachable and unavailable to another instance.
+ let index = self.instances.len();
+ if let Err(error) = self.instances.push_within_capacity(instance) {
+ self.release_instance(error.0, mm)?;
+ return Err(EIO);
+ }
+
+ let ceutils = match CeUtils::allocate(dev, cmdq, gfid, ceutils_chid) {
+ Ok(ceutils) => ceutils,
Err(error) => {
- self.release_instance(error.0, mm)?;
- Err(EIO)
+ let error = match error {
+ CeUtilsAllocError::NotOwned(error) => error,
+ CeUtilsAllocError::MayOwn(error) => {
+ dev_err!(dev, "CeUtils allocation failed: {:?}\n", error);
+ return Err(error);
+ }
+ };
+ let instance = self.instances.remove(index).map_err(|_| EIO)?;
+ self.release_instance(instance, mm)?;
+ return Err(error);
}
- }
+ };
+ let instance = self.instances.get_mut(index).ok_or(EIO)?;
+ let result = ceutils.scrub_guest_fb(dev, cmdq, bar_user, mm, &instance.vram_slot.fbmem);
+ instance.ceutils = Some(ceutils);
+ result?;
+ instance.initialized = true;
+ Ok(gfid)
}
/// Boot and configure the GSP plugin for a registered instance.
@@ -387,6 +420,9 @@ pub(super) fn activate_instance(
.iter_mut()
.find(|instance| instance.gfid == gfid)
.ok_or(ENOENT)?;
+ if !instance.initialized {
+ return Err(EINVAL);
+ }
instance.bootload(dev, cmdq, fifo_engine_list)?;
instance.plugin_rpc.init_rpc()?;
@@ -400,6 +436,7 @@ pub(super) fn destroy_instance(
&mut self,
dev: &device::Device<device::Bound>,
cmdq: &Cmdq<'_>,
+ bar_user: &BarUser<'_>,
mm: &mut GpuMm<'_>,
gfid: Gfid,
) -> Result {
@@ -408,8 +445,14 @@ pub(super) fn destroy_instance(
.iter()
.position(|instance| instance.gfid == gfid)
.ok_or(ENOENT)?;
- let instance = &mut self.instances[index];
+ let instance = self.instances.get_mut(index).ok_or(EIO)?;
+ instance.initialized = false;
instance.shutdown(dev, cmdq)?;
+ if let Some(ceutils) = instance.ceutils.as_ref() {
+ ceutils.scrub_guest_fb(dev, cmdq, bar_user, mm, &instance.vram_slot.fbmem)?;
+ }
+ instance.ceutils = None;
+ free_ceutils(dev, cmdq, gfid)?;
if instance.needs_teardown {
send_cleanup(dev, cmdq, gfid)?;
}
diff --git a/drivers/gpu/nova-core/vgpu/scrubber.rs b/drivers/gpu/nova-core/vgpu/scrubber.rs
new file mode 100644
index 000000000000..72c76fd6bbd5
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/scrubber.rs
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! Per-VM CeUtils guest framebuffer scrubbing.
+
+use kernel::{
+ device,
+ prelude::*,
+ time::{
+ delay::fsleep,
+ Delta,
+ Instant,
+ Monotonic, //
+ },
+};
+
+use crate::{
+ gsp::cmdq::Cmdq,
+ mm::{
+ bar_user::BarUser,
+ vram::VramRegion,
+ GpuMm,
+ Pfn,
+ VramAddress, //
+ },
+ vgpu::instance::Gfid, //
+};
+
+use super::commands::{
+ self,
+ CeUtilsAllocError, //
+};
+
+// Semaphore layout from OpenRM `channel_utils.h`.
+const NV_CEUTILS_SEMA_PAGE_MAGIC: u32 = 0xce5e_5ea0;
+
+#[repr(C)]
+struct CeUtilsSemaphoreHeader {
+ magic: u32,
+ payload: u32,
+}
+
+static_assert!(size_of::<CeUtilsSemaphoreHeader>() == 8);
+
+const SEMA_PAGE_MAGIC_OFFSET: usize = core::mem::offset_of!(CeUtilsSemaphoreHeader, magic);
+const SEMA_PAGE_PAYLOAD_OFFSET: usize = core::mem::offset_of!(CeUtilsSemaphoreHeader, payload);
+
+const SCRUB_REQUEST_SIZE: u64 = 4 * 1024 * 1024 * 1024;
+
+// Host timeout policy; not a firmware ABI value.
+const SCRUB_TIMEOUT: Delta = Delta::from_secs(5);
+
+/// A firmware-owned per-VM CeUtils allocation.
+///
+/// Submitted scrubs must complete before releasing this allocation or its framebuffer.
+pub(super) struct CeUtils {
+ gfid: Gfid,
+ semaphore_address: u64,
+}
+
+impl CeUtils {
+ pub(super) fn allocate(
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ gfid: Gfid,
+ chid: u32,
+ ) -> core::result::Result<Self, CeUtilsAllocError> {
+ let semaphore_address = commands::alloc_ceutils(dev, cmdq, gfid, chid)?;
+ Ok(Self {
+ gfid,
+ semaphore_address,
+ })
+ }
+
+ /// Scrub the complete guest framebuffer and wait for semaphore completion.
+ pub(super) fn scrub_guest_fb(
+ &self,
+ dev: &device::Device<device::Bound>,
+ cmdq: &Cmdq<'_>,
+ bar_user: &BarUser<'_>,
+ mm: &mut GpuMm<'_>,
+ fb: &VramRegion,
+ ) -> Result {
+ let mut offset = fb.address();
+ let end = offset.checked_add(fb.size()).ok_or(EOVERFLOW)?;
+ while offset < end {
+ let size = core::cmp::min(SCRUB_REQUEST_SIZE, end - offset);
+ let work_id = commands::submit_ceutils_scrub(dev, cmdq, self.gfid, offset, size)?;
+ wait_scrub_complete(bar_user, mm, dev, self.semaphore_address, work_id)?;
+ offset = offset.checked_add(size).ok_or(EOVERFLOW)?;
+ }
+
+ Ok(())
+ }
+}
+
+/// Poll the GSP-owned CeUtils semaphore page through a temporary BAR1 map.
+fn wait_scrub_complete(
+ bar_user: &BarUser<'_>,
+ mm: &mut GpuMm<'_>,
+ dev: &device::Device<device::Bound>,
+ semaphore_address: u64,
+ work_id: u32,
+) -> Result {
+ let pfn = Pfn::from(VramAddress::from_raw(semaphore_address));
+ let semaphore_map = bar_user.map(mm, &[pfn], false)?;
+
+ let result = (|| {
+ let magic = semaphore_map.try_read32(SEMA_PAGE_MAGIC_OFFSET)?;
+ if magic != NV_CEUTILS_SEMA_PAGE_MAGIC {
+ dev_warn!(
+ dev,
+ "bad CeUtils semaphore magic {:#x}, expected {:#x}\n",
+ magic,
+ NV_CEUTILS_SEMA_PAGE_MAGIC,
+ );
+ return Err(EIO);
+ }
+
+ let start = Instant::<Monotonic>::now();
+ loop {
+ let value = semaphore_map.try_read32(SEMA_PAGE_PAYLOAD_OFFSET)?;
+ if value.wrapping_sub(work_id) < 0x8000_0000 {
+ dev_dbg!(
+ dev,
+ "scrub completed after {:?}: semaphore={:#x}, target={:#x}\n",
+ start.elapsed(),
+ value,
+ work_id,
+ );
+ return Ok(());
+ }
+
+ if start.elapsed() >= SCRUB_TIMEOUT {
+ dev_warn!(
+ dev,
+ "scrub timed out: semaphore={:#x}, target={:#x}\n",
+ value,
+ work_id,
+ );
+ return Err(ETIMEDOUT);
+ }
+ fsleep(Delta::from_millis(1));
+ }
+ })();
+
+ let cleanup = semaphore_map.release(mm);
+ match result {
+ Ok(()) => cleanup,
+ Err(error) => {
+ if let Err(cleanup_error) = cleanup {
+ dev_err!(
+ dev,
+ "failed to release semaphore BAR1 mapping after error {:?}: {:?}\n",
+ error,
+ cleanup_error,
+ );
+ }
+ Err(error)
+ }
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 31/32] gpu: nova-core: add build ID headers to debugfs log buffer dumps
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (29 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 30/32] gpu: nova-core: vgpu: scrub guest VRAM with CeUtils Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
2026-09-14 7:49 ` [PATCH v2 32/32] gpu: nova-core: vgpu: export plugin log buffers via debugfs Zhi Wang
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Timur Tabi
From: John Hubbard <jhubbard@nvidia.com>
A raw log buffer dump cannot be decoded without knowing which firmware
build produced it, and which GPU and metadata format it belongs to.
GSP-RM's own decoder takes that from a header ahead of the data, in the
LIBOS_LOG_NVLOG_BUFFER_V2 layout.
Prepend that header to each debugfs dump. The build ID comes from the
BLID tag of gsp.tlv, so request the metadata once when the GSP manager
is created and hand it to the firmware loader rather than requesting it
again during boot. A buffer whose build ID is missing serves its
contents with no header.
zhiw: Keep this tree's borrowed DMA and command queue lifetimes and all
six LIBOS log registrations. Borrow the preloaded TLV for initialization
independently of the device lifetime. Retain the completed header byte
count if the following DMA copy fails.
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
---
drivers/gpu/nova-core/firmware.rs | 34 +++++
drivers/gpu/nova-core/firmware/gsp.rs | 16 ++-
drivers/gpu/nova-core/gpu.rs | 2 +-
drivers/gpu/nova-core/gsp.rs | 199 ++++++++++++++++++++++----
drivers/gpu/nova-core/gsp/boot.rs | 2 +-
5 files changed, 217 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index ff5b6d79de22..86c1eb459192 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -32,6 +32,40 @@
pub(crate) mod riscv;
pub(crate) mod tlv;
+/// Maximum length of a build ID, matching Open RM's `BUILD_ID_MAX_LENGTH`.
+const BUILD_ID_MAX_LENGTH: usize = 32;
+
+/// Build ID extracted from firmware, used to correlate debugfs log buffer dumps
+/// with the correct firmware symbols.
+pub(crate) struct BuildId {
+ bytes: [u8; BUILD_ID_MAX_LENGTH],
+ len: u8,
+}
+
+impl BuildId {
+ /// Constructs a [`BuildId`] from raw descriptor bytes.
+ ///
+ /// Returns `None` if `data` is empty or exceeds [`BUILD_ID_MAX_LENGTH`].
+ pub(crate) fn from_raw(data: &[u8]) -> Option<Self> {
+ if data.is_empty() || data.len() > BUILD_ID_MAX_LENGTH {
+ return None;
+ }
+
+ let mut bytes = [0u8; BUILD_ID_MAX_LENGTH];
+ bytes[..data.len()].copy_from_slice(data);
+
+ Some(Self {
+ bytes,
+ len: data.len() as u8,
+ })
+ }
+
+ /// Returns the build ID bytes.
+ pub(crate) fn as_bytes(&self) -> &[u8] {
+ &self.bytes[..usize::from(self.len)]
+ }
+}
+
/// Structure used to describe some firmwares, notably FWSEC-FRTS.
#[repr(C)]
#[derive(Debug, Clone, FromBytes)]
diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/firmware/gsp.rs
index e641f4879a42..5b2f765e77b4 100644
--- a/drivers/gpu/nova-core/firmware/gsp.rs
+++ b/drivers/gpu/nova-core/firmware/gsp.rs
@@ -6,6 +6,7 @@
Coherent,
DmaAddress, //
},
+ firmware,
prelude::*, //
};
@@ -14,8 +15,8 @@
radix3::Radix3,
riscv::RiscvFirmware, //
tlv::{
- request_tlv, //
- Tlv,
+ request_tlv,
+ Tlv, //
},
},
gpu::Chipset, //
@@ -36,13 +37,16 @@ pub(crate) struct GspFirmware<'a> {
impl<'a> GspFirmware<'a> {
/// Loads the GSP firmware binaries, map them into `dev`'s address-space, and creates the page
/// tables expected by the GSP bootloader to load it.
- pub(crate) fn new(
+ pub(crate) fn new<'fw>(
dev: &'a device::Device<device::Bound>,
chipset: Chipset,
- ) -> impl PinInit<Self, Error> + 'a {
+ gsp_tlv: &'fw firmware::Firmware,
+ ) -> impl PinInit<Self, Error> + 'fw
+ where
+ 'a: 'fw,
+ {
pin_init::pin_init_scope(move || {
- let firmware = request_tlv(dev, chipset, "gsp")?;
- let tlv = Tlv::new(firmware.data())?;
+ let tlv = Tlv::new(gsp_tlv.data())?;
dev_dbg!(dev, "loaded gsp firmware v{}\n", tlv.get_string(b"VERS")?);
let (_, fw_vvec) = tlv.load_file(dev, chipset)?;
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 61adf412bae7..a750d808fd5b 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -426,7 +426,7 @@ pub(crate) fn new<'a>(
vgpu_state: VgpuState::detect(pdev, spec.chipset, fsp.as_mut()),
- gsp <- Gsp::new(pdev, bar),
+ gsp <- Gsp::new(pdev, bar, spec.chipset),
// This member must be initialized last, so the unload bundle can never be dropped
// from outside of the constructed `GspResources`, ensuring that the unload sequence
diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs
index c961ea029fed..0bf4c8ee96ee 100644
--- a/drivers/gpu/nova-core/gsp.rs
+++ b/drivers/gpu/nova-core/gsp.rs
@@ -12,13 +12,15 @@
CoherentView,
DmaAddress, //
},
+ fs::file,
io::{
io_project,
io_write,
Io, //
},
pci,
- prelude::*, //
+ prelude::*,
+ uaccess::UserSliceWriter, //
};
pub(crate) mod cmdq;
@@ -43,6 +45,13 @@
sec2::Sec2 as Sec2Falcon,
Falcon, //
},
+ firmware::{
+ tlv::{
+ request_tlv,
+ Tlv, //
+ },
+ BuildId, //
+ },
fsp::Fsp,
gpu::Chipset,
gsp::{
@@ -101,6 +110,50 @@ fn init(view: CoherentView<'_, Self>, start: DmaAddress) -> Result<()> {
}
}
+/// Size of the header prepended to debugfs log buffer dumps.
+///
+/// This header makes each dump self-describing so that decoding tools can
+/// identify the firmware build, GPU architecture, and metadata format without
+/// out-of-band information.
+const LOG_BUFFER_HEADER_SIZE: usize = 0x48;
+
+/// Build a log buffer header from GPU and firmware metadata.
+///
+/// Layout (all little-endian):
+/// 0x00 gpuArch (u32)
+/// 0x04 gpuImpl (u32)
+/// 0x08 version (u32) = 2
+/// 0x0C buildIdLength (u32)
+/// 0x10 taskPrefix[8]
+/// 0x18 localToGlobalTimerDelta (u64) = 0
+/// 0x20 buildId[32]
+/// 0x40 flags (u32) = 1 (packed metadata)
+/// 0x44 reserved (u32) = 0
+fn build_log_buffer_header(
+ chipset: Chipset,
+ build_id: &BuildId,
+ task_prefix: &str,
+) -> [u8; LOG_BUFFER_HEADER_SIZE] {
+ let mut h = [0u8; LOG_BUFFER_HEADER_SIZE];
+ let chipset_val = chipset as u32;
+
+ h[0x00..0x04].copy_from_slice(&(chipset_val >> 4).to_le_bytes());
+ h[0x04..0x08].copy_from_slice(&(chipset_val & 0xF).to_le_bytes());
+ h[0x08..0x0C].copy_from_slice(&2u32.to_le_bytes());
+
+ let bid = build_id.as_bytes();
+ h[0x0C..0x10].copy_from_slice(&(bid.len() as u32).to_le_bytes());
+
+ let prefix = task_prefix.as_bytes();
+ let prefix_len = prefix.len().min(8);
+ h[0x10..0x10 + prefix_len].copy_from_slice(&prefix[..prefix_len]);
+
+ h[0x20..0x20 + bid.len()].copy_from_slice(bid);
+ h[0x40..0x44].copy_from_slice(&1u32.to_le_bytes());
+
+ h
+}
+
/// The logging buffers are byte queues that contain encoded printf-like
/// messages from GSP-RM. They need to be decoded by a special application
/// that can parse the buffers.
@@ -115,7 +168,13 @@ fn init(view: CoherentView<'_, Self>, start: DmaAddress) -> Result<()> {
/// then pp points to index into the buffer where the next logging entry will
/// be written. Therefore, the logging data is valid if:
/// 1 <= pp < sizeof(buffer)/sizeof(u64)
-struct LogBuffer<'a, const NUM_PAGES: usize>(Coherent<'a, [[u8; GSP_PAGE_SIZE]; NUM_PAGES]>);
+///
+/// When a build ID is available, the debugfs file for this buffer prepends
+/// a header so the dump is self-describing.
+struct LogBuffer<'a, const NUM_PAGES: usize> {
+ header: Option<[u8; LOG_BUFFER_HEADER_SIZE]>,
+ buffer: Coherent<'a, [[u8; GSP_PAGE_SIZE]; NUM_PAGES]>,
+}
/// A log buffer at the default size, [`RM_LOG_BUFFER_NUM_PAGES`] pages.
///
@@ -130,19 +189,71 @@ fn init(view: CoherentView<'_, Self>, start: DmaAddress) -> Result<()> {
impl<'a, const NUM_PAGES: usize> LogBuffer<'a, NUM_PAGES> {
/// Creates a new `LogBuffer` mapped on `dev`.
- fn new(dev: &'a device::Device<device::Bound>) -> Result<Self> {
- let obj = Self(Coherent::zeroed(dev, GFP_KERNEL)?);
-
- let start_addr = obj.0.dma_address();
-
+ fn new(
+ dev: &'a device::Device<device::Bound>,
+ chipset: Chipset,
+ build_id: Option<&BuildId>,
+ task_prefix: &str,
+ ) -> Result<Self> {
+ let buffer = Coherent::zeroed(dev, GFP_KERNEL)?;
+
+ let start_addr = buffer.dma_address();
let pte_view = io_project!(
- obj.0,
+ buffer,
[build: 0][build: size_of::<u64>()..][build: ..NUM_PAGES * size_of::<u64>()]
)
.try_cast::<PteArray<NUM_PAGES>>()?;
PteArray::init(pte_view, start_addr)?;
- Ok(obj)
+ let header = build_id.map(|bid| build_log_buffer_header(chipset, bid, task_prefix));
+
+ Ok(Self { header, buffer })
+ }
+}
+
+impl<const NUM_PAGES: usize> debugfs::BinaryWriter for LogBuffer<'_, NUM_PAGES> {
+ fn write_to_slice(
+ &self,
+ writer: &mut UserSliceWriter,
+ offset: &mut file::Offset,
+ ) -> Result<usize> {
+ if offset.is_negative() {
+ return Err(EINVAL);
+ }
+
+ let offset_val: usize = (*offset).try_into().map_err(|_| EINVAL)?;
+ let header = self.header.as_ref().map_or(&[][..], |h| h.as_slice());
+ let total_len = header.len() + self.buffer.size();
+
+ if offset_val >= total_len {
+ return Ok(0);
+ }
+
+ let count = (total_len - offset_val).min(writer.len());
+ if count == 0 {
+ return Ok(0);
+ }
+
+ let mut written = 0;
+
+ if offset_val < header.len() {
+ let hdr_count = (header.len() - offset_val).min(count);
+ writer.write_slice(&header[offset_val..offset_val + hdr_count])?;
+ written += hdr_count;
+ }
+
+ if written < count {
+ let buf_start = offset_val.saturating_sub(header.len());
+ let buf_count = count - written;
+ match writer.write_dma(&self.buffer, buf_start, buf_count) {
+ Ok(()) => written += buf_count,
+ Err(error) if written == 0 => return Err(error),
+ Err(_) => {}
+ }
+ }
+
+ *offset += written as i64;
+ Ok(written)
}
}
@@ -168,9 +279,11 @@ struct LogBuffers<'a> {
/// GSP runtime data.
#[pin_data]
pub(crate) struct Gsp<'gsp> {
+ /// Preloaded GSP firmware TLV metadata used during boot.
+ gsp_tlv: kernel::firmware::Firmware,
/// Libos arguments.
pub(crate) libos: Coherent<'gsp, [LibosMemoryRegionInitArgument]>,
- /// Log buffers, optionally exposed via debugfs.
+ /// Log buffers for all LIBOS3 tasks, exposed via debugfs.
#[pin]
logs: debugfs::Scope<LogBuffers<'gsp>>,
/// Command queue, borrowed by the GSP event interrupt handler.
@@ -187,18 +300,30 @@ impl<'gsp> Gsp<'gsp> {
pub(crate) fn new(
pdev: &'gsp pci::Device<device::Bound>,
bar: Bar0<'gsp>,
+ chipset: Chipset,
) -> impl PinInit<Self, Error> + 'gsp {
pin_init::pin_init_scope(move || {
let dev = pdev.as_ref();
- let loginit = TaskLogBuffer::new(dev)?;
- let logintr = TaskLogBuffer::new(dev)?;
- let logrm = TaskLogBuffer::new(dev)?;
- let logmnoc = TaskLogBuffer::new(dev)?;
- let logroot = SmallLogBuffer::new(dev)?;
- let logrmon = SmallLogBuffer::new(dev)?;
+ let gsp_tlv = request_tlv(dev, chipset, "gsp")?;
+ let tlv = Tlv::new(gsp_tlv.data())?;
+ let build_id = tlv.get_bytes(b"BLID").ok().and_then(BuildId::from_raw);
+ if build_id.is_none() {
+ dev_warn!(
+ pdev,
+ "GSP firmware build ID not found, log buffer headers omitted\n"
+ );
+ }
+
+ let loginit = TaskLogBuffer::new(dev, chipset, build_id.as_ref(), "INIT")?;
+ let logintr = TaskLogBuffer::new(dev, chipset, build_id.as_ref(), "INTR")?;
+ let logrm = TaskLogBuffer::new(dev, chipset, build_id.as_ref(), "RM")?;
+ let logmnoc = TaskLogBuffer::new(dev, chipset, build_id.as_ref(), "MNOC")?;
+ let logroot = SmallLogBuffer::new(dev, chipset, build_id.as_ref(), "ROOT")?;
+ let logrmon = SmallLogBuffer::new(dev, chipset, build_id.as_ref(), "RMON")?;
Ok(try_pin_init!(Self {
+ gsp_tlv,
cmdq <- Cmdq::new(dev, bar),
rm_state_monitor: Coherent::zeroed(dev, GFP_KERNEL)?,
rmargs: Coherent::init(
@@ -213,12 +338,30 @@ pub(crate) fn new(
GFP_KERNEL,
)?;
- libos.init_at(0, LibosMemoryRegionInitArgument::new("LOGINIT", &loginit.0))?;
- libos.init_at(1, LibosMemoryRegionInitArgument::new("LOGINTR", &logintr.0))?;
- libos.init_at(2, LibosMemoryRegionInitArgument::new("LOGRM", &logrm.0))?;
- libos.init_at(3, LibosMemoryRegionInitArgument::new("LOGMNOC", &logmnoc.0))?;
- libos.init_at(4, LibosMemoryRegionInitArgument::new("LOGROOT", &logroot.0))?;
- libos.init_at(5, LibosMemoryRegionInitArgument::new("LOGRMON", &logrmon.0))?;
+ libos.init_at(
+ 0,
+ LibosMemoryRegionInitArgument::new("LOGINIT", &loginit.buffer),
+ )?;
+ libos.init_at(
+ 1,
+ LibosMemoryRegionInitArgument::new("LOGINTR", &logintr.buffer),
+ )?;
+ libos.init_at(
+ 2,
+ LibosMemoryRegionInitArgument::new("LOGRM", &logrm.buffer),
+ )?;
+ libos.init_at(
+ 3,
+ LibosMemoryRegionInitArgument::new("LOGMNOC", &logmnoc.buffer),
+ )?;
+ libos.init_at(
+ 4,
+ LibosMemoryRegionInitArgument::new("LOGROOT", &logroot.buffer),
+ )?;
+ libos.init_at(
+ 5,
+ LibosMemoryRegionInitArgument::new("LOGRMON", &logrmon.buffer),
+ )?;
libos.init_at(6, LibosMemoryRegionInitArgument::new("RMARGS", rmargs))?;
libos.into()
@@ -244,12 +387,12 @@ pub(crate) fn new(
.expect("DEBUGFS_ROOT not initialized");
log_parent.scope(log_buffers, dev.name(), |logs, dir| {
- dir.read_binary_file(c"loginit", &logs.loginit.0);
- dir.read_binary_file(c"logintr", &logs.logintr.0);
- dir.read_binary_file(c"logrm", &logs.logrm.0);
- dir.read_binary_file(c"logmnoc", &logs.logmnoc.0);
- dir.read_binary_file(c"logroot", &logs.logroot.0);
- dir.read_binary_file(c"logrmon", &logs.logrmon.0);
+ dir.read_binary_file(c"loginit", &logs.loginit);
+ dir.read_binary_file(c"logintr", &logs.logintr);
+ dir.read_binary_file(c"logrm", &logs.logrm);
+ dir.read_binary_file(c"logmnoc", &logs.logmnoc);
+ dir.read_binary_file(c"logroot", &logs.logroot);
+ dir.read_binary_file(c"logrmon", &logs.logrmon);
})
},
}))
diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs
index fa879685bac5..a35a25cac9db 100644
--- a/drivers/gpu/nova-core/gsp/boot.rs
+++ b/drivers/gpu/nova-core/gsp/boot.rs
@@ -77,7 +77,7 @@ pub(crate) fn boot(
let dev = pdev.as_ref();
let hal = super::hal::gsp_hal(chipset);
- let gsp_fw = KBox::pin_init(GspFirmware::new(dev, chipset), GFP_KERNEL)?;
+ let gsp_fw = KBox::pin_init(GspFirmware::new(dev, chipset, &self.gsp_tlv), GFP_KERNEL)?;
// GSP-RM reads the ucodes image through a radix3 page table, so the mapping has to
// outlive initialization.
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH v2 32/32] gpu: nova-core: vgpu: export plugin log buffers via debugfs
2026-09-14 7:48 [PATCH v2 00/32] Introduce NVIDIA vGPU manager Zhi Wang
` (30 preceding siblings ...)
2026-09-14 7:49 ` [PATCH v2 31/32] gpu: nova-core: add build ID headers to debugfs log buffer dumps Zhi Wang
@ 2026-09-14 7:49 ` Zhi Wang
31 siblings, 0 replies; 33+ messages in thread
From: Zhi Wang @ 2026-09-14 7:49 UTC (permalink / raw)
To: dakr, acourbot
Cc: alex, jgg, yishaih, skolothumtho, kevin.tian, airlied, simona,
ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh, lossin,
a.hindborg, aliceryhl, tmgross, jhubbard, ecourtney, cjia,
smitra, kjaju, alkumar, ankita, aniketa, kwankhede, targupta,
nova-gpu, linux-kernel, zhiwang, Zhi Wang
Expose the three per-VM GSP plugin log buffers (init, vgpu, kernel)
through debugfs so that nvlog_decoder can decode them at runtime.
Each log file is backed by VRAM in the management heap and read via
BAR1 MMIO. Prepend the GSP log header when a firmware build ID is
available.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp.rs | 4 +-
drivers/gpu/nova-core/mm/bar_user.rs | 5 +-
drivers/gpu/nova-core/vgpu.rs | 1 +
drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 120 +++++++++++-
drivers/gpu/nova-core/vgpu/instance.rs | 77 +++++++-
drivers/gpu/nova-core/vgpu/log.rs | 171 ++++++++++++++++++
6 files changed, 364 insertions(+), 14 deletions(-)
create mode 100644 drivers/gpu/nova-core/vgpu/log.rs
diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs
index 0bf4c8ee96ee..96ee879ce268 100644
--- a/drivers/gpu/nova-core/gsp.rs
+++ b/drivers/gpu/nova-core/gsp.rs
@@ -115,7 +115,7 @@ fn init(view: CoherentView<'_, Self>, start: DmaAddress) -> Result<()> {
/// This header makes each dump self-describing so that decoding tools can
/// identify the firmware build, GPU architecture, and metadata format without
/// out-of-band information.
-const LOG_BUFFER_HEADER_SIZE: usize = 0x48;
+pub(crate) const LOG_BUFFER_HEADER_SIZE: usize = 0x48;
/// Build a log buffer header from GPU and firmware metadata.
///
@@ -129,7 +129,7 @@ fn init(view: CoherentView<'_, Self>, start: DmaAddress) -> Result<()> {
/// 0x20 buildId[32]
/// 0x40 flags (u32) = 1 (packed metadata)
/// 0x44 reserved (u32) = 0
-fn build_log_buffer_header(
+pub(crate) fn build_log_buffer_header(
chipset: Chipset,
build_id: &BuildId,
task_prefix: &str,
diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs
index b7b4bf14b56d..2e9482256b16 100644
--- a/drivers/gpu/nova-core/mm/bar_user.rs
+++ b/drivers/gpu/nova-core/mm/bar_user.rs
@@ -188,7 +188,6 @@ pub(crate) struct BarMapping<'map, 'gpu> {
logical_size: usize,
}
-#[expect(dead_code)]
impl<'map, 'gpu> BarMapping<'map, 'gpu> {
/// Maps the containing pages while restricting CPU access to the requested byte range.
pub(crate) fn new(
@@ -231,6 +230,10 @@ pub(crate) fn new(
})
}
+ pub(crate) fn bar1(&self) -> &'gpu Bar1<'gpu> {
+ self.access.bar_user.bar1
+ }
+
pub(crate) fn region(&self) -> &VramRegion {
&self.region
}
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 407accc05139..123f5a20986e 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -28,6 +28,7 @@
mod gsp_plugin_rpc;
mod hal;
mod instance;
+mod log;
mod scrubber;
mod vram;
diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
index e385ecff43fa..7aa9e9caaa49 100644
--- a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
+++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs
@@ -3,15 +3,21 @@
//! GSP plugin communication buffer mappings and access.
-use kernel::prelude::*;
+use kernel::{
+ io::Io,
+ prelude::*, //
+};
-use crate::mm::{
- bar_user::{
- BarMapping,
- BarUser, //
+use crate::{
+ driver::Bar1,
+ mm::{
+ bar_user::{
+ BarMapping,
+ BarUser, //
+ },
+ vram::VramRegion,
+ GpuMm, //
},
- vram::VramRegion,
- GpuMm, //
};
use super::fw::{
@@ -50,6 +56,97 @@ fn take_region(region: &VramRegion, cursor: &mut u64, size: u32) -> Result<VramR
Ok(subregion)
}
+/// BAR1 view of one vGPU plugin log buffer.
+pub(super) struct MappedPluginLogBuffer<'gpu> {
+ bar1: &'gpu Bar1<'gpu>,
+ gpu_va_addr: usize,
+ size: usize,
+}
+
+impl<'gpu> MappedPluginLogBuffer<'gpu> {
+ fn new(map: &BarMapping<'_, 'gpu>, region: &VramRegion) -> Result<Self> {
+ let start = region
+ .address()
+ .checked_sub(map.region().address())
+ .ok_or(EINVAL)
+ .and_then(|start| usize::try_from(start).map_err(|_| EOVERFLOW))?;
+ let size = usize::try_from(region.size()).map_err(|_| EOVERFLOW)?;
+ let end = start.checked_add(size).ok_or(EOVERFLOW)?;
+ if end > map.size() || !start.is_multiple_of(4) || !size.is_multiple_of(4) {
+ return Err(EINVAL);
+ }
+
+ let gpu_va_addr = usize::try_from(map.gpu_va_addr()?)
+ .map_err(|_| EOVERFLOW)?
+ .checked_add(start)
+ .ok_or(EOVERFLOW)?;
+ if !gpu_va_addr.is_multiple_of(4) {
+ return Err(EINVAL);
+ }
+
+ let bar1 = map.bar1();
+ if gpu_va_addr.checked_add(size).ok_or(EOVERFLOW)? > bar1.size() {
+ return Err(EINVAL);
+ }
+
+ Ok(Self {
+ bar1,
+ gpu_va_addr,
+ size,
+ })
+ }
+
+ pub(super) const fn size(&self) -> usize {
+ self.size
+ }
+
+ pub(super) fn read(&self, offset: usize, output: &mut [u8]) -> Result {
+ let end = offset.checked_add(output.len()).ok_or(EOVERFLOW)?;
+ if end > self.size {
+ return Err(EINVAL);
+ }
+
+ let mut source = offset;
+ let mut copied = 0usize;
+
+ while copied < output.len() {
+ let aligned_source = source & !3;
+ let within = source & 3;
+ let bar_offset = self
+ .gpu_va_addr
+ .checked_add(aligned_source)
+ .ok_or(EOVERFLOW)?;
+ let bytes = self.bar1.try_read32(bar_offset)?.to_le_bytes();
+ let chunk = (4 - within).min(output.len() - copied);
+
+ output[copied..copied + chunk].copy_from_slice(&bytes[within..within + chunk]);
+ source = source.checked_add(chunk).ok_or(EOVERFLOW)?;
+ copied += chunk;
+ }
+
+ Ok(())
+ }
+}
+
+/// BAR1 views of all vGPU plugin log buffers.
+pub(super) struct MappedPluginLogBuffers<'gpu> {
+ init: MappedPluginLogBuffer<'gpu>,
+ vgpu: MappedPluginLogBuffer<'gpu>,
+ kernel: MappedPluginLogBuffer<'gpu>,
+}
+
+impl<'gpu> MappedPluginLogBuffers<'gpu> {
+ pub(super) fn into_parts(
+ self,
+ ) -> (
+ MappedPluginLogBuffer<'gpu>,
+ MappedPluginLogBuffer<'gpu>,
+ MappedPluginLogBuffer<'gpu>,
+ ) {
+ (self.init, self.vgpu, self.kernel)
+ }
+}
+
/// BAR1 mapping of the plugin communication region in its management heap.
///
/// r000 layout, with byte offsets from the management heap (not to scale):
@@ -216,6 +313,15 @@ pub(super) fn plugin_logs(&self) -> PluginLogRegions {
}
}
+ /// Return BAR1 views that must stop being read before this mapping is destroyed.
+ pub(super) fn mapped_plugin_logs(&self) -> Result<MappedPluginLogBuffers<'gpu>> {
+ Ok(MappedPluginLogBuffers {
+ init: MappedPluginLogBuffer::new(&self.map, &self.init_log)?,
+ vgpu: MappedPluginLogBuffer::new(&self.map, &self.vgpu_log)?,
+ kernel: MappedPluginLogBuffer::new(&self.map, &self.kernel_log)?,
+ })
+ }
+
/// Clear a previous boot marker before starting the plugin.
pub(super) fn clear_plugin_ready(&self) -> Result {
let offset = self.io_offset(
diff --git a/drivers/gpu/nova-core/vgpu/instance.rs b/drivers/gpu/nova-core/vgpu/instance.rs
index bb01d4088b5e..7f47c158d407 100644
--- a/drivers/gpu/nova-core/vgpu/instance.rs
+++ b/drivers/gpu/nova-core/vgpu/instance.rs
@@ -4,10 +4,12 @@
use core::num::NonZeroUsize;
use kernel::{
+ debugfs,
device,
prelude::*,
ptr::Alignment,
- sizes::SizeConstants, //
+ sizes::SizeConstants,
+ str::CString, //
time::{
delay::fsleep,
Delta,
@@ -23,7 +25,11 @@
use crate::{
driver::Bar0,
- gpu::ChannelIdReservation,
+ firmware::BuildId,
+ gpu::{
+ ChannelIdReservation,
+ Chipset, //
+ },
mm::{
bar_user::BarUser,
GpuMm, //
@@ -31,8 +37,12 @@
};
use super::{
- gsp_plugin_comm::CommBufferRegion,
+ gsp_plugin_comm::{
+ CommBufferRegion,
+ MappedPluginLogBuffers, //
+ },
gsp_plugin_rpc::PluginRpc,
+ log::VgpuLogBuffers,
scrubber::CeUtils,
vram::{
VgpuVramLayout,
@@ -143,6 +153,7 @@ pub(super) struct VgpuInstance<'gpu> {
vm_pid: u32,
chids: ChannelIdReservation<'gpu>,
num_plugin_channels: u32,
+ debugfs_logs: Option<Pin<KBox<debugfs::Scope<VgpuLogBuffers<'gpu>>>>>,
vram_slot: VgpuVramSlot,
pub(super) plugin_rpc: PluginRpc<'gpu, 'gpu>,
ceutils: Option<CeUtils>,
@@ -246,6 +257,39 @@ pub(super) const fn new(gfid: Gfid, dbdf: Dbdf, vgpu_type: VgpuType, vm_pid: u32
}
}
+fn create_debugfs_logs<'gpu>(
+ buffers: MappedPluginLogBuffers<'gpu>,
+ dbdf: Dbdf,
+ chipset: Chipset,
+ build_id: Option<&BuildId>,
+) -> Result<Pin<KBox<debugfs::Scope<VgpuLogBuffers<'gpu>>>>> {
+ let logs = VgpuLogBuffers::new(buffers, chipset, build_id);
+ let raw_dbdf = dbdf.into_raw();
+ let domain = raw_dbdf >> 16;
+ let bus = (raw_dbdf >> 8) & 0xff;
+ let device = (raw_dbdf >> 3) & 0x1f;
+ let function = raw_dbdf & 0x07;
+ let directory = CString::try_from_fmt(fmt!(
+ "{:04x}:{:02x}:{:02x}.{:x}-vgpu",
+ domain,
+ bus,
+ device,
+ function,
+ ))?;
+
+ #[allow(static_mut_refs)]
+ // SAFETY: The root is initialized before driver registration and cleared
+ // only after driver unregistration has drained all users.
+ let root = unsafe { crate::DEBUGFS_ROOT.as_ref() }.ok_or(ENODEV)?;
+
+ KBox::pin_init(
+ root.scope(logs, &directory, |logs, directory| {
+ VgpuLogBuffers::register_debugfs(logs, directory);
+ }),
+ GFP_KERNEL,
+ )
+}
+
/// Registry of live vGPU instances.
pub(super) struct VgpuInstances<'gpu> {
instances: KVec<VgpuInstance<'gpu>>,
@@ -287,10 +331,12 @@ fn release_vram_slot(&mut self, slot: VgpuVramSlot) -> Result {
fn release_instance(&mut self, instance: VgpuInstance<'gpu>, mm: &mut GpuMm<'_>) -> Result {
let VgpuInstance {
+ debugfs_logs,
plugin_rpc,
vram_slot,
..
} = instance;
+ drop(debugfs_logs);
let result = plugin_rpc.destroy(mm);
self.release_vram_slot(vram_slot)?;
result
@@ -369,6 +415,7 @@ pub(super) fn allocate_instance(
vm_pid,
chids,
num_plugin_channels: 3,
+ debugfs_logs: None,
vram_slot,
plugin_rpc: PluginRpc::new(comm),
ceutils: None,
@@ -407,6 +454,7 @@ pub(super) fn allocate_instance(
}
/// Boot and configure the GSP plugin for a registered instance.
+ #[expect(clippy::too_many_arguments)]
pub(super) fn activate_instance(
&mut self,
dev: &device::Device<device::Bound>,
@@ -414,6 +462,8 @@ pub(super) fn activate_instance(
bar0: Bar0<'_>,
gfid: Gfid,
fifo_engine_list: &FifoEngineList,
+ chipset: Chipset,
+ build_id: Option<&BuildId>,
) -> Result {
let instance = self
.instances
@@ -428,7 +478,26 @@ pub(super) fn activate_instance(
instance.plugin_rpc.init_rpc()?;
negotiate_plugin_version(dev, bar0, gfid, &mut instance.plugin_rpc)?;
instance.configure_plugin(dev, bar0)?;
- set_plugin_bme(dev, bar0, gfid, &mut instance.plugin_rpc, true)
+ set_plugin_bme(dev, bar0, gfid, &mut instance.plugin_rpc, true)?;
+
+ if instance.debugfs_logs.is_none() {
+ match instance
+ .plugin_rpc
+ .comm()
+ .mapped_plugin_logs()
+ .and_then(|buffers| create_debugfs_logs(buffers, instance.dbdf, chipset, build_id))
+ {
+ Ok(logs) => instance.debugfs_logs = Some(logs),
+ Err(error) => dev_warn!(
+ dev,
+ "debugfs logs unavailable for gfid={}: {:?}\n",
+ gfid.0,
+ error,
+ ),
+ }
+ }
+
+ Ok(())
}
/// Stop the plugin and release the instance's firmware and host resources.
diff --git a/drivers/gpu/nova-core/vgpu/log.rs b/drivers/gpu/nova-core/vgpu/log.rs
new file mode 100644
index 000000000000..6f58f8ae9bf0
--- /dev/null
+++ b/drivers/gpu/nova-core/vgpu/log.rs
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! GSP plugin logs exposed through debugfs.
+//!
+//! With debugfs mounted at `/sys/kernel/debug`, the directory uses the VF's
+//! PCI domain:bus:device.function address:
+//!
+//! ```text
+//! /sys/kernel/debug/nova-core/<VF-DBDF>-vgpu/
+//! |-- init_log
+//! |-- vgpu_log
+//! `-- kernel_log
+//! ```
+
+use kernel::{
+ debugfs,
+ fs::file,
+ prelude::*,
+ uaccess::UserSliceWriter, //
+};
+
+use crate::{
+ firmware::BuildId,
+ gpu::Chipset,
+ gsp::{
+ build_log_buffer_header,
+ LOG_BUFFER_HEADER_SIZE, //
+ },
+ vgpu::gsp_plugin_comm::{
+ MappedPluginLogBuffer,
+ MappedPluginLogBuffers, //
+ },
+};
+
+const LOG_READ_CHUNK_SIZE: usize = 4096;
+
+/// A vGPU plugin log buffer backed by VRAM, read via BAR1 MMIO.
+///
+/// An optional header lets `nvlog_decoder` identify the GPU architecture and firmware build.
+struct VgpuLogBuffer<'gpu> {
+ buffer: MappedPluginLogBuffer<'gpu>,
+ header: [u8; LOG_BUFFER_HEADER_SIZE],
+ header_len: usize,
+}
+
+impl<'gpu> VgpuLogBuffer<'gpu> {
+ fn new(
+ buffer: MappedPluginLogBuffer<'gpu>,
+ chipset: Chipset,
+ build_id: Option<&BuildId>,
+ task_prefix: &str,
+ ) -> Self {
+ let (header, header_len) = match build_id {
+ Some(bid) => (
+ build_log_buffer_header(chipset, bid, task_prefix),
+ LOG_BUFFER_HEADER_SIZE,
+ ),
+ None => ([0u8; LOG_BUFFER_HEADER_SIZE], 0),
+ };
+
+ Self {
+ buffer,
+ header,
+ header_len,
+ }
+ }
+}
+
+impl debugfs::BinaryWriter for VgpuLogBuffer<'_> {
+ fn write_to_slice(
+ &self,
+ writer: &mut UserSliceWriter,
+ offset: &mut file::Offset,
+ ) -> Result<usize> {
+ if offset.is_negative() {
+ return Err(EINVAL);
+ }
+
+ let offset_val: usize = (*offset).try_into().map_err(|_| EINVAL)?;
+ let total_len = self
+ .header_len
+ .checked_add(self.buffer.size())
+ .ok_or(EOVERFLOW)?;
+
+ if offset_val >= total_len {
+ return Ok(0);
+ }
+
+ let count = (total_len - offset_val).min(writer.len());
+ if count == 0 {
+ return Ok(0);
+ }
+
+ // Keep the staging buffer on the heap to avoid a page-sized kernel stack object.
+ let staging_size = count.min(LOG_READ_CHUNK_SIZE);
+ let mut staging = KVec::new();
+ staging.resize(staging_size, 0, GFP_KERNEL)?;
+
+ let mut written = 0usize;
+ let result: Result = (|| {
+ while written < count {
+ let chunk_len = (count - written).min(staging.len());
+ let chunk = &mut staging[..chunk_len];
+ let chunk_offset = offset_val.checked_add(written).ok_or(EOVERFLOW)?;
+ let mut filled = 0usize;
+
+ if chunk_offset < self.header_len {
+ let header_len = (self.header_len - chunk_offset).min(chunk_len);
+ chunk[..header_len]
+ .copy_from_slice(&self.header[chunk_offset..chunk_offset + header_len]);
+ filled = header_len;
+ }
+
+ if filled < chunk_len {
+ let log_offset = chunk_offset
+ .checked_add(filled)
+ .ok_or(EOVERFLOW)?
+ .checked_sub(self.header_len)
+ .ok_or(EINVAL)?;
+
+ self.buffer.read(log_offset, &mut chunk[filled..])?;
+ }
+
+ writer.write_slice(chunk)?;
+ written = written.checked_add(chunk_len).ok_or(EOVERFLOW)?;
+ }
+ Ok(())
+ })();
+ if written == 0 {
+ result?;
+ }
+
+ *offset = (*offset)
+ .checked_add(i64::try_from(written).map_err(|_| EOVERFLOW)?)
+ .ok_or(EOVERFLOW)?;
+ Ok(written)
+ }
+}
+
+/// The three plugin log streams for one vGPU instance.
+pub(super) struct VgpuLogBuffers<'gpu> {
+ init_log: VgpuLogBuffer<'gpu>,
+ vgpu_log: VgpuLogBuffer<'gpu>,
+ kernel_log: VgpuLogBuffer<'gpu>,
+}
+
+impl<'gpu> VgpuLogBuffers<'gpu> {
+ pub(super) fn new(
+ buffers: MappedPluginLogBuffers<'gpu>,
+ chipset: Chipset,
+ build_id: Option<&BuildId>,
+ ) -> Self {
+ let (init, vgpu, kernel) = buffers.into_parts();
+
+ Self {
+ init_log: VgpuLogBuffer::new(init, chipset, build_id, "INIT"),
+ vgpu_log: VgpuLogBuffer::new(vgpu, chipset, build_id, "VGPU"),
+ kernel_log: VgpuLogBuffer::new(kernel, chipset, build_id, "KERN"),
+ }
+ }
+
+ pub(super) fn register_debugfs<'data, 'dir>(
+ logs: &'data Self,
+ dir: &'dir debugfs::ScopedDir<'data, 'dir>,
+ ) {
+ dir.read_binary_file(c"init_log", &logs.init_log);
+ dir.read_binary_file(c"vgpu_log", &logs.vgpu_log);
+ dir.read_binary_file(c"kernel_log", &logs.kernel_log);
+ }
+}
^ permalink raw reply [flat|nested] 33+ messages in thread