[PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic

[PATCH v2 00/19] riscv: andes: make the LLC driver and cache errata generic

[Mina Hui-Min Chou]

The Andes last level cache (LLC) driver and the Andes cache errata were
written for the AX45MP core in the Renesas RZ/Five. Other Andes cores use
the same LLC controller and need the same CCTL-based cache maintenance,
but the driver, its binding and the errata only handle AX45MP.

This series makes them generic, in preparation for the Allwinner V821
SoC [1][2], which uses the Andes A27L2 core [3]. The A27L2 has neither
IOCP nor Zicbom, so it relies on the LLC driver for DMA cache
maintenance.

The series is organized as follows:

- Patches 2-6 rename the AX45MP and L2 identifiers to generic Andes and
  LLC names, move the Andes CSR definitions to a shared header, and
  rename ax45mp_cache.c to andes_llcache.c. No functional change.

- Patches 1, 7 and 8 are small cleanups. No functional change.

- Patches 9-11 fix issues that do not show up on RZ/Five but affect
  other Andes platforms:
  - write the full physical address to the 64-bit CCTL registers,
  - register the CCTL cache ops only when the errata asks for them, so
    that they do not override Zicbom CMO,
  - index the per-core CCTL registers by hart ID, not logical CPU
    number.

- Patches 12-15 add andestech,llcache as a generic compatible, keep
  andestech,ax45mp-cache for existing devicetrees, and add a
  MAINTAINERS entry for the driver.

- Patches 16-18 make the Andes cache errata usable on any Andes SoC:
  ERRATA_ANDES_CMO no longer depends on ARCH_R9A07G043, Andes cores
  other than AX45MP use the CCTL ops when they do not implement Zicbom,
  and the SBI-based IOCP check is limited to RZ/Five.

- Patch 19 adds the andestech,a27l2 CPU compatible. The V821 devicetree
  will be submitted separately by Allwinner.

Existing RZ/Five devicetrees and behavior are unchanged.

[1] https://www.allwinnertech.com/index.php?c=product&a=index&id=136
[2] https://github.com/AvaotaSBC/AvaotaF1
[3] https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a27l2/

Changes in v2:
- Rework the series: split the refactoring into smaller patches, drop
  the performance and feature changes, and add the cache errata
  changes needed for other Andes cores.
- Split the v1 refactoring patch into separate rename, header, macro
  and file rename patches.
- Keep andestech,ax45mp-cache and add andestech,llcache as a generic
  fallback compatible, instead of renaming the compatible. Drop the v1
  DTS update patch accordingly.
- Drop the performance and feature changes of v1 patches 2/7-4/7 to
  keep this series focused on making the driver generic. They will be
  sent separately.
- New: fix the CCTL physical address width, the cache ops registration
  condition and the CCTL register index (patches 9-11).
- New: generalize the Andes cache errata (patches 16-18).
- New: add the A27L2 CPU compatible (patch 19).
- Link to v1: https://lore.kernel.org/r/20260330102724.1012470-1-minachou@andestech.com

Mina Hui-Min Chou (19):
  cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops
  cache: ax45mp_cache: rename AX45MP-specific identifiers to generic
    ANDES
  cache: ax45mp_cache: rename L2 identifiers to LLC
  cache: ax45mp_cache: add shared header for Andes CSRs
  cache: ax45mp_cache: standardize macro naming for LLC and L1D
    registers
  cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c
  cache: andes_llcache: clean up cache inv/wback functions
  cache: andes_llcache: use u32 and fix the cache-line-size error
    message
  cache: andes_llcache: write the full physical address for CCTL
  cache: andes_llcache: register cache ops only when the errata needs
    them
  cache: andes_llcache: use the hart ID to index the CCTL registers
  dt-bindings: cache: andestech: update schema for generic LLC support
  dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache
  cache: andes_llcache: add generic andestech,llcache compatible
  MAINTAINERS: Add maintainer for Andes cache driver
  riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs
  riscv: errata: andes: generalize cache errata for Andes cores
  riscv: errata: andes: limit the IOCP workaround to RZ/Five
  dt-bindings: riscv: add Andes A27L2 CPU compatible

 ...45mp-cache.yaml => andestech,llcache.yaml} |  73 ++++--
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 MAINTAINERS                                   |   7 +
 arch/riscv/Kconfig.errata                     |   6 +-
 arch/riscv/errata/andes/errata.c              |  22 +-
 arch/riscv/include/asm/errata_list_vendors.h  |   2 +-
 drivers/cache/Kconfig                         |   9 +-
 drivers/cache/Makefile                        |   2 +-
 drivers/cache/andes_llcache.c                 | 213 +++++++++++++++++
 drivers/cache/ax45mp_cache.c                  | 217 ------------------
 drivers/soc/renesas/Kconfig                   |   2 +-
 include/linux/soc/andes/csr.h                 |  12 +
 12 files changed, 316 insertions(+), 250 deletions(-)
 rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,llcache.yaml} (52%)
 create mode 100644 drivers/cache/andes_llcache.c
 delete mode 100644 drivers/cache/ax45mp_cache.c
 create mode 100644 include/linux/soc/andes/csr.h


base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
-- 
2.34.1

[PATCH v2 01/19] cache: ax45mp_cache: use __initconst for ax45mp_cmo_ops

[Mina Hui-Min Chou]

ax45mp_cmo_ops is const, but is placed in .init.data with __initdata.
Const init data belongs in .init.rodata, so annotate it with
__initconst instead.

riscv_noncoherent_register_cache_ops() copies the ops into
noncoherent_cache_ops, so the struct is still not used after init.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/ax45mp_cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 934c5087ec2b..df40dea7b0d9 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -165,7 +165,7 @@ static int ax45mp_get_l2_line_size(struct device_node *np)
 	return 0;
 }
 
-static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initdata = {
+static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initconst = {
 	.wback = &ax45mp_dma_cache_wback,
 	.inv = &ax45mp_dma_cache_inv,
 	.wback_inv = &ax45mp_dma_cache_wback_inv,
-- 
2.34.1

[PATCH v2 02/19] cache: ax45mp_cache: rename AX45MP-specific identifiers to generic ANDES

[Mina Hui-Min Chou]

The Andes cache driver is not limited to AX45MP; it can also be used
with other Andes CPUs such as the A27L2. To prepare for SoC support
(Allwinner V821 with an A27L2 CPU), rename all AX45MP-specific
identifiers to use generic ANDES prefixes.

This is a mechanical rename with no functional change:
- Kconfig: AX45MP_L2_CACHE -> ANDES_LLCACHE
- struct: ax45mp_priv -> andes_priv
- macros: AX45MP_* -> ANDES_*
- functions: ax45mp_cpu_* -> andes_cpu_*

Update the Kconfig prompt and help text to match, and re-align the
continuation lines affected by the shorter function names.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/Kconfig        |   9 ++-
 drivers/cache/Makefile       |   2 +-
 drivers/cache/ax45mp_cache.c | 142 +++++++++++++++++------------------
 drivers/soc/renesas/Kconfig  |   2 +-
 4 files changed, 79 insertions(+), 76 deletions(-)

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1518449d47b5..68e6e4aead21 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -10,11 +10,14 @@ menuconfig CACHEMAINT_FOR_DMA
 
 if CACHEMAINT_FOR_DMA
 
-config AX45MP_L2_CACHE
-	bool "Andes Technology AX45MP L2 Cache controller"
+config ANDES_LLCACHE
+	bool "Andes last level cache controller"
 	select RISCV_NONSTANDARD_CACHE_OPS
 	help
-	  Support for the L2 cache controller on Andes Technology AX45MP platforms.
+	  Support for the cache controller of Andes CPU cores such as the
+	  AX45MP and A27L2. It provides cache maintenance operations on the
+	  L1 data cache and the last level cache (LLC), which are needed for
+	  non-coherent DMA on cores without the standard Zicbom extension.
 
 config SIFIVE_CCACHE
 	bool "Sifive Composable Cache controller"
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index b3362b15d6c1..290aa238b2e2 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_AX45MP_L2_CACHE)		+= ax45mp_cache.o
+obj-$(CONFIG_ANDES_LLCACHE)		+= ax45mp_cache.o
 obj-$(CONFIG_SIFIVE_CCACHE)		+= sifive_ccache.o
 obj-$(CONFIG_STARFIVE_STARLINK_CACHE)	+= starfive_starlink_cache.o
 
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index df40dea7b0d9..4f9b8a9ad969 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * non-coherent cache functions for Andes AX45MP
+ * non-coherent cache operations for Andes Platform CPUs
  *
  * Copyright (C) 2023 Renesas Electronics Corp.
  */
@@ -14,72 +14,72 @@
 #include <asm/dma-noncoherent.h>
 
 /* L2 cache registers */
-#define AX45MP_L2C_REG_CTL_OFFSET		0x8
+#define ANDES_L2C_REG_CTL_OFFSET		0x8
 
-#define AX45MP_L2C_REG_C0_CMD_OFFSET		0x40
-#define AX45MP_L2C_REG_C0_ACC_OFFSET		0x48
-#define AX45MP_L2C_REG_STATUS_OFFSET		0x80
+#define ANDES_L2C_REG_C0_CMD_OFFSET		0x40
+#define ANDES_L2C_REG_C0_ACC_OFFSET		0x48
+#define ANDES_L2C_REG_STATUS_OFFSET		0x80
 
 /* D-cache operation */
-#define AX45MP_CCTL_L1D_VA_INVAL		0 /* Invalidate an L1 cache entry */
-#define AX45MP_CCTL_L1D_VA_WB			1 /* Write-back an L1 cache entry */
+#define ANDES_CCTL_L1D_VA_INVAL		0 /* Invalidate an L1 cache entry */
+#define ANDES_CCTL_L1D_VA_WB			1 /* Write-back an L1 cache entry */
 
 /* L2 CCTL status */
-#define AX45MP_CCTL_L2_STATUS_IDLE		0
+#define ANDES_CCTL_L2_STATUS_IDLE		0
 
 /* L2 CCTL status cores mask */
-#define AX45MP_CCTL_L2_STATUS_C0_MASK		0xf
+#define ANDES_CCTL_L2_STATUS_C0_MASK		0xf
 
 /* L2 cache operation */
-#define AX45MP_CCTL_L2_PA_INVAL			0x8 /* Invalidate an L2 cache entry */
-#define AX45MP_CCTL_L2_PA_WB			0x9 /* Write-back an L2 cache entry */
+#define ANDES_CCTL_L2_PA_INVAL			0x8 /* Invalidate an L2 cache entry */
+#define ANDES_CCTL_L2_PA_WB			0x9 /* Write-back an L2 cache entry */
 
-#define AX45MP_L2C_REG_PER_CORE_OFFSET		0x10
-#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET	4
+#define ANDES_L2C_REG_PER_CORE_OFFSET		0x10
+#define ANDES_CCTL_L2_STATUS_PER_CORE_OFFSET	4
 
-#define AX45MP_L2C_REG_CN_CMD_OFFSET(n)	\
-	(AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
-#define AX45MP_L2C_REG_CN_ACC_OFFSET(n)	\
-	(AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
-#define AX45MP_CCTL_L2_STATUS_CN_MASK(n)	\
-	(AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET))
+#define ANDES_L2C_REG_CN_CMD_OFFSET(n)	\
+	(ANDES_L2C_REG_C0_CMD_OFFSET + ((n) * ANDES_L2C_REG_PER_CORE_OFFSET))
+#define ANDES_L2C_REG_CN_ACC_OFFSET(n)	\
+	(ANDES_L2C_REG_C0_ACC_OFFSET + ((n) * ANDES_L2C_REG_PER_CORE_OFFSET))
+#define ANDES_CCTL_L2_STATUS_CN_MASK(n)	\
+	(ANDES_CCTL_L2_STATUS_C0_MASK << ((n) * ANDES_CCTL_L2_STATUS_PER_CORE_OFFSET))
 
-#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM	0x80b
-#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM	0x80c
+#define ANDES_CCTL_REG_UCCTLBEGINADDR_NUM	0x80b
+#define ANDES_CCTL_REG_UCCTLCOMMAND_NUM	0x80c
 
-#define AX45MP_CACHE_LINE_SIZE			64
+#define ANDES_CACHE_LINE_SIZE			64
 
-struct ax45mp_priv {
+struct andes_priv {
 	void __iomem *l2c_base;
-	u32 ax45mp_cache_line_size;
+	u32 andes_cache_line_size;
 };
 
-static struct ax45mp_priv ax45mp_priv;
+static struct andes_priv andes_priv;
 
 /* L2 Cache operations */
-static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void)
+static inline uint32_t andes_cpu_l2c_get_cctl_status(void)
 {
-	return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET);
+	return readl(andes_priv.l2c_base + ANDES_L2C_REG_STATUS_OFFSET);
 }
 
-static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
-				       unsigned int l1_op, unsigned int l2_op)
+static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
+				      unsigned int l1_op, unsigned int l2_op)
 {
-	unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size;
-	void __iomem *base = ax45mp_priv.l2c_base;
+	unsigned long line_size = andes_priv.andes_cache_line_size;
+	void __iomem *base = andes_priv.l2c_base;
 	int mhartid = smp_processor_id();
 	unsigned long pa;
 
 	while (end > start) {
-		csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);
-		csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
+		csr_write(ANDES_CCTL_REG_UCCTLBEGINADDR_NUM, start);
+		csr_write(ANDES_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
 
 		pa = virt_to_phys((void *)start);
-		writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
-		writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
-		while ((ax45mp_cpu_l2c_get_cctl_status() &
-			AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
-			AX45MP_CCTL_L2_STATUS_IDLE)
+		writel(pa, base + ANDES_L2C_REG_CN_ACC_OFFSET(mhartid));
+		writel(l2_op, base + ANDES_L2C_REG_CN_CMD_OFFSET(mhartid));
+		while ((andes_cpu_l2c_get_cctl_status() &
+			ANDES_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
+			ANDES_CCTL_L2_STATUS_IDLE)
 			;
 
 		start += line_size;
@@ -87,20 +87,20 @@ static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
 }
 
 /* Write-back L1 and L2 cache entry */
-static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end)
+static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
 {
-	ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB,
-				   AX45MP_CCTL_L2_PA_WB);
+	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_WB,
+				  ANDES_CCTL_L2_PA_WB);
 }
 
 /* Invalidate the L1 and L2 cache entry */
-static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end)
+static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
 {
-	ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL,
-				   AX45MP_CCTL_L2_PA_INVAL);
+	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_INVAL,
+				  ANDES_CCTL_L2_PA_INVAL);
 }
 
-static void ax45mp_dma_cache_inv(phys_addr_t paddr, size_t size)
+static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
 	unsigned long start = (unsigned long)phys_to_virt(paddr);
 	unsigned long end = start + size;
@@ -110,19 +110,19 @@ static void ax45mp_dma_cache_inv(phys_addr_t paddr, size_t size)
 	if (unlikely(start == end))
 		return;
 
-	line_size = ax45mp_priv.ax45mp_cache_line_size;
+	line_size = andes_priv.andes_cache_line_size;
 
 	start = start & (~(line_size - 1));
 	end = ((end + line_size - 1) & (~(line_size - 1)));
 
 	local_irq_save(flags);
 
-	ax45mp_cpu_dcache_inval_range(start, end);
+	andes_cpu_dcache_inval_range(start, end);
 
 	local_irq_restore(flags);
 }
 
-static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
+static void andes_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	unsigned long start = (unsigned long)phys_to_virt(paddr);
 	unsigned long end = start + size;
@@ -132,57 +132,57 @@ static void ax45mp_dma_cache_wback(phys_addr_t paddr, size_t size)
 	if (unlikely(start == end))
 		return;
 
-	line_size = ax45mp_priv.ax45mp_cache_line_size;
+	line_size = andes_priv.andes_cache_line_size;
 	start = start & (~(line_size - 1));
 	end = ((end + line_size - 1) & (~(line_size - 1)));
 	local_irq_save(flags);
-	ax45mp_cpu_dcache_wb_range(start, end);
+	andes_cpu_dcache_wb_range(start, end);
 	local_irq_restore(flags);
 }
 
-static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 {
-	ax45mp_dma_cache_wback(paddr, size);
-	ax45mp_dma_cache_inv(paddr, size);
+	andes_dma_cache_wback(paddr, size);
+	andes_dma_cache_inv(paddr, size);
 }
 
-static int ax45mp_get_l2_line_size(struct device_node *np)
+static int andes_get_l2_line_size(struct device_node *np)
 {
 	int ret;
 
-	ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size);
+	ret = of_property_read_u32(np, "cache-line-size", &andes_priv.andes_cache_line_size);
 	if (ret) {
 		pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
 		return ret;
 	}
 
-	if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) {
+	if (andes_priv.andes_cache_line_size != ANDES_CACHE_LINE_SIZE) {
 		pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
-		       ax45mp_priv.ax45mp_cache_line_size);
+		       andes_priv.andes_cache_line_size);
 		return -EINVAL;
 	}
 
 	return 0;
 }
 
-static const struct riscv_nonstd_cache_ops ax45mp_cmo_ops __initconst = {
-	.wback = &ax45mp_dma_cache_wback,
-	.inv = &ax45mp_dma_cache_inv,
-	.wback_inv = &ax45mp_dma_cache_wback_inv,
+static const struct riscv_nonstd_cache_ops andes_cmo_ops __initconst = {
+	.wback = &andes_dma_cache_wback,
+	.inv = &andes_dma_cache_inv,
+	.wback_inv = &andes_dma_cache_wback_inv,
 };
 
-static const struct of_device_id ax45mp_cache_ids[] = {
+static const struct of_device_id andes_cache_ids[] = {
 	{ .compatible = "andestech,ax45mp-cache" },
 	{ /* sentinel */ }
 };
 
-static int __init ax45mp_cache_init(void)
+static int __init andes_cache_init(void)
 {
 	struct resource res;
 	int ret;
 
 	struct device_node *np __free(device_node) =
-		of_find_matching_node(NULL, ax45mp_cache_ids);
+		of_find_matching_node(NULL, andes_cache_ids);
 	if (!of_device_is_available(np))
 		return -ENODEV;
 
@@ -191,7 +191,7 @@ static int __init ax45mp_cache_init(void)
 		return ret;
 
 	/*
-	 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
+	 * If IOCP is present on the Andes core riscv_cbom_block_size
 	 * will be 0 for sure, so we can definitely rely on it. If
 	 * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
 	 * more so we just return success here and only if its being set we
@@ -200,18 +200,18 @@ static int __init ax45mp_cache_init(void)
 	if (!riscv_cbom_block_size)
 		return 0;
 
-	ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res));
-	if (!ax45mp_priv.l2c_base)
+	andes_priv.l2c_base = ioremap(res.start, resource_size(&res));
+	if (!andes_priv.l2c_base)
 		return -ENOMEM;
 
-	ret = ax45mp_get_l2_line_size(np);
+	ret = andes_get_l2_line_size(np);
 	if (ret) {
-		iounmap(ax45mp_priv.l2c_base);
+		iounmap(andes_priv.l2c_base);
 		return ret;
 	}
 
-	riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops);
+	riscv_noncoherent_register_cache_ops(&andes_cmo_ops);
 
 	return 0;
 }
-early_initcall(ax45mp_cache_init);
+early_initcall(andes_cache_init);
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index a63df28df3b5..b36265d53ebb 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -465,7 +465,7 @@ config ARCH_R9A07G043
 	depends on !RISCV_ISA_ZICBOM
 	depends on RISCV_SBI
 	select ARCH_RZG2L
-	select AX45MP_L2_CACHE
+	select ANDES_LLCACHE
 	select CACHEMAINT_FOR_DMA
 	select DMA_GLOBAL_POOL
 	select ERRATA_ANDES
-- 
2.34.1

[PATCH v2 03/19] cache: ax45mp_cache: rename L2 identifiers to LLC

[Mina Hui-Min Chou]

Rename all L2-related identifiers to LLC to accurately reflect the
cache's role as the system's last-level cache.

This is a mechanical rename with no functional change:
- macros: ANDES_L2C_* -> ANDES_LLC_*
- struct: l2c_base -> llc_base
- function: andes_*_l2_*() -> andes_*_llc_*()
- comments: L2 cache -> LLC

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/ax45mp_cache.c | 80 ++++++++++++++++++------------------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 4f9b8a9ad969..0ee8218d5a82 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -13,36 +13,36 @@
 
 #include <asm/dma-noncoherent.h>
 
-/* L2 cache registers */
-#define ANDES_L2C_REG_CTL_OFFSET		0x8
+/* LLC registers */
+#define ANDES_LLC_REG_CTL_OFFSET		0x8
 
-#define ANDES_L2C_REG_C0_CMD_OFFSET		0x40
-#define ANDES_L2C_REG_C0_ACC_OFFSET		0x48
-#define ANDES_L2C_REG_STATUS_OFFSET		0x80
+#define ANDES_LLC_REG_C0_CMD_OFFSET		0x40
+#define ANDES_LLC_REG_C0_ACC_OFFSET		0x48
+#define ANDES_LLC_REG_STATUS_OFFSET		0x80
 
 /* D-cache operation */
 #define ANDES_CCTL_L1D_VA_INVAL		0 /* Invalidate an L1 cache entry */
 #define ANDES_CCTL_L1D_VA_WB			1 /* Write-back an L1 cache entry */
 
-/* L2 CCTL status */
-#define ANDES_CCTL_L2_STATUS_IDLE		0
+/* LLC CCTL status */
+#define ANDES_CCTL_LLC_STATUS_IDLE		0
 
-/* L2 CCTL status cores mask */
-#define ANDES_CCTL_L2_STATUS_C0_MASK		0xf
+/* LLC CCTL status cores mask */
+#define ANDES_CCTL_LLC_STATUS_C0_MASK		0xf
 
-/* L2 cache operation */
-#define ANDES_CCTL_L2_PA_INVAL			0x8 /* Invalidate an L2 cache entry */
-#define ANDES_CCTL_L2_PA_WB			0x9 /* Write-back an L2 cache entry */
+/* LLC operation */
+#define ANDES_CCTL_LLC_PA_INVAL			0x8 /* Invalidate an LLC entry */
+#define ANDES_CCTL_LLC_PA_WB			0x9 /* Write-back an LLC entry */
 
-#define ANDES_L2C_REG_PER_CORE_OFFSET		0x10
-#define ANDES_CCTL_L2_STATUS_PER_CORE_OFFSET	4
+#define ANDES_LLC_REG_PER_CORE_OFFSET		0x10
+#define ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET	4
 
-#define ANDES_L2C_REG_CN_CMD_OFFSET(n)	\
-	(ANDES_L2C_REG_C0_CMD_OFFSET + ((n) * ANDES_L2C_REG_PER_CORE_OFFSET))
-#define ANDES_L2C_REG_CN_ACC_OFFSET(n)	\
-	(ANDES_L2C_REG_C0_ACC_OFFSET + ((n) * ANDES_L2C_REG_PER_CORE_OFFSET))
-#define ANDES_CCTL_L2_STATUS_CN_MASK(n)	\
-	(ANDES_CCTL_L2_STATUS_C0_MASK << ((n) * ANDES_CCTL_L2_STATUS_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CN_CMD_OFFSET(n)	\
+	(ANDES_LLC_REG_C0_CMD_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CN_ACC_OFFSET(n)	\
+	(ANDES_LLC_REG_C0_ACC_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
+#define ANDES_CCTL_LLC_STATUS_CN_MASK(n)	\
+	(ANDES_CCTL_LLC_STATUS_C0_MASK << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
 
 #define ANDES_CCTL_REG_UCCTLBEGINADDR_NUM	0x80b
 #define ANDES_CCTL_REG_UCCTLCOMMAND_NUM	0x80c
@@ -50,23 +50,23 @@
 #define ANDES_CACHE_LINE_SIZE			64
 
 struct andes_priv {
-	void __iomem *l2c_base;
+	void __iomem *llc_base;
 	u32 andes_cache_line_size;
 };
 
 static struct andes_priv andes_priv;
 
-/* L2 Cache operations */
-static inline uint32_t andes_cpu_l2c_get_cctl_status(void)
+/* LLC operations */
+static inline uint32_t andes_cpu_llc_get_cctl_status(void)
 {
-	return readl(andes_priv.l2c_base + ANDES_L2C_REG_STATUS_OFFSET);
+	return readl(andes_priv.llc_base + ANDES_LLC_REG_STATUS_OFFSET);
 }
 
 static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
-				      unsigned int l1_op, unsigned int l2_op)
+				      unsigned int l1_op, unsigned int llc_op)
 {
 	unsigned long line_size = andes_priv.andes_cache_line_size;
-	void __iomem *base = andes_priv.l2c_base;
+	void __iomem *base = andes_priv.llc_base;
 	int mhartid = smp_processor_id();
 	unsigned long pa;
 
@@ -75,29 +75,29 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 		csr_write(ANDES_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
 
 		pa = virt_to_phys((void *)start);
-		writel(pa, base + ANDES_L2C_REG_CN_ACC_OFFSET(mhartid));
-		writel(l2_op, base + ANDES_L2C_REG_CN_CMD_OFFSET(mhartid));
-		while ((andes_cpu_l2c_get_cctl_status() &
-			ANDES_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
-			ANDES_CCTL_L2_STATUS_IDLE)
+		writel(pa, base + ANDES_LLC_REG_CN_ACC_OFFSET(mhartid));
+		writel(llc_op, base + ANDES_LLC_REG_CN_CMD_OFFSET(mhartid));
+		while ((andes_cpu_llc_get_cctl_status() &
+			ANDES_CCTL_LLC_STATUS_CN_MASK(mhartid)) !=
+			ANDES_CCTL_LLC_STATUS_IDLE)
 			;
 
 		start += line_size;
 	}
 }
 
-/* Write-back L1 and L2 cache entry */
+/* Write-back L1 and LLC entry */
 static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
 {
 	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_WB,
-				  ANDES_CCTL_L2_PA_WB);
+				  ANDES_CCTL_LLC_PA_WB);
 }
 
-/* Invalidate the L1 and L2 cache entry */
+/* Invalidate the L1 and LLC entry */
 static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
 {
 	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_INVAL,
-				  ANDES_CCTL_L2_PA_INVAL);
+				  ANDES_CCTL_LLC_PA_INVAL);
 }
 
 static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
@@ -146,7 +146,7 @@ static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 	andes_dma_cache_inv(paddr, size);
 }
 
-static int andes_get_l2_line_size(struct device_node *np)
+static int andes_get_llc_line_size(struct device_node *np)
 {
 	int ret;
 
@@ -200,13 +200,13 @@ static int __init andes_cache_init(void)
 	if (!riscv_cbom_block_size)
 		return 0;
 
-	andes_priv.l2c_base = ioremap(res.start, resource_size(&res));
-	if (!andes_priv.l2c_base)
+	andes_priv.llc_base = ioremap(res.start, resource_size(&res));
+	if (!andes_priv.llc_base)
 		return -ENOMEM;
 
-	ret = andes_get_l2_line_size(np);
+	ret = andes_get_llc_line_size(np);
 	if (ret) {
-		iounmap(andes_priv.l2c_base);
+		iounmap(andes_priv.llc_base);
 		return ret;
 	}
 
-- 
2.34.1

[PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs

[Mina Hui-Min Chou]

Add linux/soc/andes/csr.h as a central place for Andes vendor-specific
CSR definitions, and update the cache driver to use CSR_UCCTLBEGINADDR
and CSR_UCCTLCOMMAND from the new header instead of local definitions.
More Andes CSR definitions will be added here as needed.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/ax45mp_cache.c  |  8 +++-----
 include/linux/soc/andes/csr.h | 12 ++++++++++++
 2 files changed, 15 insertions(+), 5 deletions(-)
 create mode 100644 include/linux/soc/andes/csr.h

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 0ee8218d5a82..b3d6f6a11cfc 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -10,6 +10,7 @@
 #include <linux/dma-direction.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/soc/andes/csr.h>
 
 #include <asm/dma-noncoherent.h>
 
@@ -44,9 +45,6 @@
 #define ANDES_CCTL_LLC_STATUS_CN_MASK(n)	\
 	(ANDES_CCTL_LLC_STATUS_C0_MASK << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
 
-#define ANDES_CCTL_REG_UCCTLBEGINADDR_NUM	0x80b
-#define ANDES_CCTL_REG_UCCTLCOMMAND_NUM	0x80c
-
 #define ANDES_CACHE_LINE_SIZE			64
 
 struct andes_priv {
@@ -71,8 +69,8 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 	unsigned long pa;
 
 	while (end > start) {
-		csr_write(ANDES_CCTL_REG_UCCTLBEGINADDR_NUM, start);
-		csr_write(ANDES_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
+		csr_write(CSR_UCCTLBEGINADDR, start);
+		csr_write(CSR_UCCTLCOMMAND, l1_op);
 
 		pa = virt_to_phys((void *)start);
 		writel(pa, base + ANDES_LLC_REG_CN_ACC_OFFSET(mhartid));
diff --git a/include/linux/soc/andes/csr.h b/include/linux/soc/andes/csr.h
new file mode 100644
index 000000000000..3214b4b08a46
--- /dev/null
+++ b/include/linux/soc/andes/csr.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2026 Andes Technology Corporation.
+ */
+#ifndef __LINUX_SOC_ANDES_CSR_H
+#define __LINUX_SOC_ANDES_CSR_H
+
+/* User mode control registers */
+#define CSR_UCCTLBEGINADDR		0x80b
+#define CSR_UCCTLCOMMAND		0x80c
+
+#endif /* !__LINUX_SOC_ANDES_CSR_H */
-- 
2.34.1

[PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers

[Mina Hui-Min Chou]

Rename macros to follow a consistent naming convention:
ANDES_{LLC|L1D}_{REG_}CCTL_{operation}_{target}
- LLC or L1D: which cache level
- REG_: present for register offset macros
- CCTL: cache control operation
- target: C0 for core 0 base, BY_CORE(n) for per-core variants

This is a mechanical rename with no functional change:
- ANDES_LLC_REG_C0_* -> ANDES_LLC_REG_CCTL_*_C0
- ANDES_LLC_REG_CN_* -> ANDES_LLC_REG_CCTL_*_BY_CORE(n)
- ANDES_CCTL_L1D_*   -> ANDES_L1D_CCTL_*
- ANDES_CCTL_LLC_*   -> ANDES_LLC_CCTL_*
- Use GENMASK(3, 0) instead of 0xf for ANDES_LLC_CCTL_STATUS_MASK_C0

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/ax45mp_cache.c | 55 ++++++++++++++++++------------------
 1 file changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index b3d6f6a11cfc..61730e218afa 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -16,34 +16,33 @@
 
 /* LLC registers */
 #define ANDES_LLC_REG_CTL_OFFSET		0x8
+#define ANDES_LLC_REG_CCTL_CMD_OFFSET_C0	0x40
+#define ANDES_LLC_REG_CCTL_ACC_OFFSET_C0	0x48
+#define ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0	0x80
 
-#define ANDES_LLC_REG_C0_CMD_OFFSET		0x40
-#define ANDES_LLC_REG_C0_ACC_OFFSET		0x48
-#define ANDES_LLC_REG_STATUS_OFFSET		0x80
-
-/* D-cache operation */
-#define ANDES_CCTL_L1D_VA_INVAL		0 /* Invalidate an L1 cache entry */
-#define ANDES_CCTL_L1D_VA_WB			1 /* Write-back an L1 cache entry */
+/* L1 D-cache operation */
+#define ANDES_L1D_CCTL_VA_INVAL			0x0 /* Invalidate an L1 cache entry */
+#define ANDES_L1D_CCTL_VA_WB			0x1 /* Write-back an L1 cache entry */
 
 /* LLC CCTL status */
-#define ANDES_CCTL_LLC_STATUS_IDLE		0
+#define ANDES_LLC_CCTL_STATUS_IDLE		0x0
 
 /* LLC CCTL status cores mask */
-#define ANDES_CCTL_LLC_STATUS_C0_MASK		0xf
+#define ANDES_LLC_CCTL_STATUS_MASK_C0		GENMASK(3, 0)
 
 /* LLC operation */
-#define ANDES_CCTL_LLC_PA_INVAL			0x8 /* Invalidate an LLC entry */
-#define ANDES_CCTL_LLC_PA_WB			0x9 /* Write-back an LLC entry */
+#define ANDES_LLC_CCTL_PA_INVAL			0x8 /* Invalidate an LLC entry */
+#define ANDES_LLC_CCTL_PA_WB			0x9 /* Write-back an LLC entry */
 
-#define ANDES_LLC_REG_PER_CORE_OFFSET		0x10
-#define ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET	4
+#define ANDES_LLC_REG_CCTL_CORE_OFFSET		0x10
+#define ANDES_LLC_CCTL_STATUS_MASK_CORE_OFFSET	0x4
 
-#define ANDES_LLC_REG_CN_CMD_OFFSET(n)	\
-	(ANDES_LLC_REG_C0_CMD_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
-#define ANDES_LLC_REG_CN_ACC_OFFSET(n)	\
-	(ANDES_LLC_REG_C0_ACC_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
-#define ANDES_CCTL_LLC_STATUS_CN_MASK(n)	\
-	(ANDES_CCTL_LLC_STATUS_C0_MASK << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(n)	\
+	(ANDES_LLC_REG_CCTL_CMD_OFFSET_C0 + ((n) * ANDES_LLC_REG_CCTL_CORE_OFFSET))
+#define ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(n)	\
+	(ANDES_LLC_REG_CCTL_ACC_OFFSET_C0 + ((n) * ANDES_LLC_REG_CCTL_CORE_OFFSET))
+#define ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(n)	\
+	(ANDES_LLC_CCTL_STATUS_MASK_C0 << ((n) * ANDES_LLC_CCTL_STATUS_MASK_CORE_OFFSET))
 
 #define ANDES_CACHE_LINE_SIZE			64
 
@@ -57,7 +56,7 @@ static struct andes_priv andes_priv;
 /* LLC operations */
 static inline uint32_t andes_cpu_llc_get_cctl_status(void)
 {
-	return readl(andes_priv.llc_base + ANDES_LLC_REG_STATUS_OFFSET);
+	return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
 }
 
 static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
@@ -73,11 +72,11 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 		csr_write(CSR_UCCTLCOMMAND, l1_op);
 
 		pa = virt_to_phys((void *)start);
-		writel(pa, base + ANDES_LLC_REG_CN_ACC_OFFSET(mhartid));
-		writel(llc_op, base + ANDES_LLC_REG_CN_CMD_OFFSET(mhartid));
+		writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
+		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
 		while ((andes_cpu_llc_get_cctl_status() &
-			ANDES_CCTL_LLC_STATUS_CN_MASK(mhartid)) !=
-			ANDES_CCTL_LLC_STATUS_IDLE)
+			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
+			ANDES_LLC_CCTL_STATUS_IDLE)
 			;
 
 		start += line_size;
@@ -87,15 +86,15 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 /* Write-back L1 and LLC entry */
 static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
 {
-	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_WB,
-				  ANDES_CCTL_LLC_PA_WB);
+	andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_WB,
+				  ANDES_LLC_CCTL_PA_WB);
 }
 
 /* Invalidate the L1 and LLC entry */
 static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
 {
-	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_INVAL,
-				  ANDES_CCTL_LLC_PA_INVAL);
+	andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_INVAL,
+				  ANDES_LLC_CCTL_PA_INVAL);
 }
 
 static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
-- 
2.34.1

[PATCH v2 06/19] cache: ax45mp_cache: rename ax45mp_cache.c to andes_llcache.c

[Mina Hui-Min Chou]

Rename to reflect the generic Andes naming. No functional change.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/Makefile                            | 2 +-
 drivers/cache/{ax45mp_cache.c => andes_llcache.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename drivers/cache/{ax45mp_cache.c => andes_llcache.c} (100%)

diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 290aa238b2e2..7c342111ea51 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_ANDES_LLCACHE)		+= ax45mp_cache.o
+obj-$(CONFIG_ANDES_LLCACHE)		+= andes_llcache.o
 obj-$(CONFIG_SIFIVE_CCACHE)		+= sifive_ccache.o
 obj-$(CONFIG_STARFIVE_STARLINK_CACHE)	+= starfive_starlink_cache.o
 
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/andes_llcache.c
similarity index 100%
rename from drivers/cache/ax45mp_cache.c
rename to drivers/cache/andes_llcache.c
-- 
2.34.1

[PATCH v2 07/19] cache: andes_llcache: clean up cache inv/wback functions

[Mina Hui-Min Chou]

Replace open-coded cache line alignment with ALIGN_DOWN/ALIGN helpers,
initialize line_size at declaration site, and use !size instead of
start == end for the early-out check. Drop redundant blank lines.

Also declare pa in andes_cpu_cache_operation() as phys_addr_t, the type
virt_to_phys() returns.

No functional change intended.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 61730e218afa..3c271e1e49bf 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -65,7 +65,7 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 	unsigned long line_size = andes_priv.andes_cache_line_size;
 	void __iomem *base = andes_priv.llc_base;
 	int mhartid = smp_processor_id();
-	unsigned long pa;
+	phys_addr_t pa;
 
 	while (end > start) {
 		csr_write(CSR_UCCTLBEGINADDR, start);
@@ -101,21 +101,17 @@ static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
 	unsigned long start = (unsigned long)phys_to_virt(paddr);
 	unsigned long end = start + size;
-	unsigned long line_size;
+	unsigned long line_size = andes_priv.andes_cache_line_size;
 	unsigned long flags;
 
-	if (unlikely(start == end))
+	if (unlikely(!size))
 		return;
 
-	line_size = andes_priv.andes_cache_line_size;
-
-	start = start & (~(line_size - 1));
-	end = ((end + line_size - 1) & (~(line_size - 1)));
+	start = ALIGN_DOWN(start, line_size);
+	end = ALIGN(end, line_size);
 
 	local_irq_save(flags);
-
 	andes_cpu_dcache_inval_range(start, end);
-
 	local_irq_restore(flags);
 }
 
@@ -123,15 +119,15 @@ static void andes_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	unsigned long start = (unsigned long)phys_to_virt(paddr);
 	unsigned long end = start + size;
-	unsigned long line_size;
+	unsigned long line_size = andes_priv.andes_cache_line_size;
 	unsigned long flags;
 
-	if (unlikely(start == end))
+	if (unlikely(!size))
 		return;
 
-	line_size = andes_priv.andes_cache_line_size;
-	start = start & (~(line_size - 1));
-	end = ((end + line_size - 1) & (~(line_size - 1)));
+	start = ALIGN_DOWN(start, line_size);
+	end = ALIGN(end, line_size);
+
 	local_irq_save(flags);
 	andes_cpu_dcache_wb_range(start, end);
 	local_irq_restore(flags);
-- 
2.34.1

[PATCH v2 08/19] cache: andes_llcache: use u32 and fix the cache-line-size error message

[Mina Hui-Min Chou]

andes_cpu_llc_get_cctl_status() returns uint32_t, while the rest of the
driver uses u32. Use u32 there as well.

When the cache-line-size property cannot be read, the error message
says the driver defaults to 64 bytes, but the driver returns the error
and does not register its cache ops. Drop the misleading part of the
message.

No functional change intended.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 3c271e1e49bf..0aea1389f291 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -54,7 +54,7 @@ struct andes_priv {
 static struct andes_priv andes_priv;
 
 /* LLC operations */
-static inline uint32_t andes_cpu_llc_get_cctl_status(void)
+static inline u32 andes_cpu_llc_get_cctl_status(void)
 {
 	return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
 }
@@ -145,7 +145,7 @@ static int andes_get_llc_line_size(struct device_node *np)
 
 	ret = of_property_read_u32(np, "cache-line-size", &andes_priv.andes_cache_line_size);
 	if (ret) {
-		pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
+		pr_err("Failed to get cache-line-size\n");
 		return ret;
 	}
 
-- 
2.34.1

[PATCH v2 09/19] cache: andes_llcache: write the full physical address for CCTL

[Mina Hui-Min Chou]

The CCTL access line registers are 64 bits wide and hold the physical
address for PA-type CCTL operations, but the driver writes them with
writel(). On RV64, a physical address above 4 GiB loses its upper 32
bits, and the LLC operates on the wrong line.

Write the register with writeq(), using the lo-hi helper on RV32, so
that the whole physical address is always written.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 0aea1389f291..bf49dbcb080b 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -8,6 +8,7 @@
 #include <linux/cacheflush.h>
 #include <linux/cacheinfo.h>
 #include <linux/dma-direction.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/soc/andes/csr.h>
@@ -72,7 +73,8 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 		csr_write(CSR_UCCTLCOMMAND, l1_op);
 
 		pa = virt_to_phys((void *)start);
-		writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
+		/* The access line register is 64 bits; written lo-hi on RV32 */
+		writeq(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
 		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
 		while ((andes_cpu_llc_get_cctl_status() &
 			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
-- 
2.34.1

[PATCH v2 10/19] cache: andes_llcache: register cache ops only when the errata needs them

[Mina Hui-Min Chou]

The driver registers its CCTL-based cache ops whenever
riscv_cbom_block_size is non-zero. On Andes cores with Zicbom, it holds
the Zicbom block size, so the CCTL ops would override the standard
Zicbom CMO.

Only register them when riscv_cbom_block_size is 1, the value the Andes
errata sets when the core needs CCTL-based cache maintenance.

Do this check before looking up the LLC node, so the driver does
nothing on platforms that do not need it. Once the errata has asked for
the CCTL ops, the LLC node is required to provide them, so report a
missing node with an error instead of failing silently.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index bf49dbcb080b..80c55616ab10 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -176,25 +176,25 @@ static int __init andes_cache_init(void)
 	struct resource res;
 	int ret;
 
+	/*
+	 * The Andes errata sets riscv_cbom_block_size to 1 only when the
+	 * core needs CCTL-based cache maintenance. Otherwise this driver is
+	 * not needed, so return without probing it any further.
+	 */
+	if (riscv_cbom_block_size != 1)
+		return 0;
+
 	struct device_node *np __free(device_node) =
 		of_find_matching_node(NULL, andes_cache_ids);
-	if (!of_device_is_available(np))
+	if (!of_device_is_available(np)) {
+		pr_err("No Andes LLC node found, cache ops not registered\n");
 		return -ENODEV;
+	}
 
 	ret = of_address_to_resource(np, 0, &res);
 	if (ret)
 		return ret;
 
-	/*
-	 * If IOCP is present on the Andes core riscv_cbom_block_size
-	 * will be 0 for sure, so we can definitely rely on it. If
-	 * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
-	 * more so we just return success here and only if its being set we
-	 * continue further in the probe path.
-	 */
-	if (!riscv_cbom_block_size)
-		return 0;
-
 	andes_priv.llc_base = ioremap(res.start, resource_size(&res));
 	if (!andes_priv.llc_base)
 		return -ENOMEM;
-- 
2.34.1

[PATCH v2 11/19] cache: andes_llcache: use the hart ID to index the CCTL registers

[Mina Hui-Min Chou]

The LLC has a separate set of CCTL registers for each core, selected by
the hart ID of the core. The driver selects the set with
smp_processor_id(), which returns the logical CPU number, not the hart
ID.

The two numbers differ when some harts are not used by Linux, or when
Linux boots on a hart other than 0, as the boot hart is always CPU 0.
A CPU then issues its LLC operations through the registers of another
hart, which may be in use by that hart at the same time.

RZ/Five has a single core with hart ID 0, so the two numbers always
match there and the problem never showed up.

Convert the logical CPU number to the hart ID with
cpuid_to_hartid_map().

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 80c55616ab10..9f8fa8964302 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -65,7 +65,7 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 {
 	unsigned long line_size = andes_priv.andes_cache_line_size;
 	void __iomem *base = andes_priv.llc_base;
-	int mhartid = smp_processor_id();
+	unsigned long hartid = cpuid_to_hartid_map(smp_processor_id());
 	phys_addr_t pa;
 
 	while (end > start) {
@@ -74,10 +74,10 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 
 		pa = virt_to_phys((void *)start);
 		/* The access line register is 64 bits; written lo-hi on RV32 */
-		writeq(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
-		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
+		writeq(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(hartid));
+		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(hartid));
 		while ((andes_cpu_llc_get_cctl_status() &
-			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
+			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(hartid)) !=
 			ANDES_LLC_CCTL_STATUS_IDLE)
 			;
 
-- 
2.34.1

[PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support

[Mina Hui-Min Chou]

The last level cache controller of Andes cores is not specific to
AX45MP. Other Andes cores, such as the A27L2, use the same controller
with the same register interface, but the binding only accepts
andestech,ax45mp-cache. Add andestech,llcache for them, and describe
the binding as an Andes last level cache rather than an AX45MP L2
cache.

The cache-level, cache-sets and cache-size constraints describe the
AX45MP L2 cache, so apply them to andestech,ax45mp-cache only. The LLC
of other Andes cores can be level 3 and have other geometries, so
allow cache-level 3 and require cache-sets only for AX45MP. Match
renesas,r9a07g043f-ax45mp-cache explicitly instead of through the else
branch, which would otherwise also apply to andestech,llcache.

Also add an example for andestech,llcache, and add myself as a
maintainer of the binding.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 .../cache/andestech,ax45mp-cache.yaml         | 71 ++++++++++++++-----
 1 file changed, 54 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index b135ffa4ab6b..da9688cc95f7 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -5,14 +5,15 @@
 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Andestech AX45MP L2 Cache Controller
+title: Andestech Last Level Cache Controller
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+  - Mina Hui-Min Chou <minachou@andestech.com>
 
 description:
-  A level-2 cache (L2C) is used to improve the system performance by providing
-  a large amount of cache line entries and reasonable access delays. The L2C
+  A last level cache (LLC) is used to improve the system performance by providing
+  a large amount of cache line entries and reasonable access delays. The LLC
   is shared between cores, and a non-inclusive non-exclusive policy is used.
 
 select:
@@ -21,18 +22,23 @@ select:
       contains:
         enum:
           - andestech,ax45mp-cache
+          - andestech,llcache
 
   required:
     - compatible
 
 properties:
   compatible:
-    items:
-      - enum:
-          - andestech,qilai-ax45mp-cache
-          - renesas,r9a07g043f-ax45mp-cache
-      - const: andestech,ax45mp-cache
-      - const: cache
+    oneOf:
+      - items:
+          - enum:
+              - andestech,qilai-ax45mp-cache
+              - renesas,r9a07g043f-ax45mp-cache
+          - const: andestech,ax45mp-cache
+          - const: cache
+      - items:
+          - const: andestech,llcache
+          - const: cache
 
   reg:
     maxItems: 1
@@ -44,13 +50,11 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
-  cache-sets:
-    enum: [1024, 2048]
+  cache-sets: true
 
-  cache-size:
-    enum: [131072, 262144, 524288, 1048576, 2097152]
+  cache-size: true
 
   cache-unified: true
 
@@ -64,7 +68,6 @@ required:
   - interrupts
   - cache-line-size
   - cache-level
-  - cache-sets
   - cache-size
   - cache-unified
 
@@ -73,15 +76,36 @@ allOf:
       properties:
         compatible:
           contains:
-            const: andestech,qilai-ax45mp-cache
+            const: andestech,ax45mp-cache
+    then:
+      properties:
+        cache-level:
+          const: 2
+        cache-sets:
+          enum: [1024, 2048]
+        cache-size:
+          enum: [131072, 262144, 524288, 1048576, 2097152]
+      required:
+        - cache-sets
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: andestech,qilai-ax45mp-cache
     then:
       properties:
         cache-sets:
           const: 2048
         cache-size:
           const: 2097152
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043f-ax45mp-cache
+    then:
       properties:
         cache-sets:
           const: 1024
@@ -101,3 +125,16 @@ examples:
         cache-size = <262144>;
         cache-unified;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    cache-controller@e0500000 {
+        compatible = "andestech,llcache", "cache";
+        reg = <0xe0500000 0x10000>;
+        interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+        cache-line-size = <64>;
+        cache-level = <2>;
+        cache-size = <262144>;
+        cache-unified;
+    };
-- 
2.34.1

[PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache

[Mina Hui-Min Chou]

The binding now covers Andes last level caches beyond AX45MP and uses
andestech,llcache as the generic compatible. Rename the file to match
it.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 .../{andestech,ax45mp-cache.yaml => andestech,llcache.yaml}     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,llcache.yaml} (97%)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,llcache.yaml
similarity index 97%
rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
rename to Documentation/devicetree/bindings/cache/andestech,llcache.yaml
index da9688cc95f7..f97038d39b0e 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,llcache.yaml
@@ -2,7 +2,7 @@
 # Copyright (C) 2023 Renesas Electronics Corp.
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
+$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Andestech Last Level Cache Controller
-- 
2.34.1

[PATCH v2 14/19] cache: andes_llcache: add generic andestech,llcache compatible

[Mina Hui-Min Chou]

Add andestech,llcache as a generic fallback compatible string.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 drivers/cache/andes_llcache.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c
index 9f8fa8964302..17df8b8af9d4 100644
--- a/drivers/cache/andes_llcache.c
+++ b/drivers/cache/andes_llcache.c
@@ -168,6 +168,7 @@ static const struct riscv_nonstd_cache_ops andes_cmo_ops __initconst = {
 
 static const struct of_device_id andes_cache_ids[] = {
 	{ .compatible = "andestech,ax45mp-cache" },
+	{ .compatible = "andestech,llcache" },
 	{ /* sentinel */ }
 };
 
-- 
2.34.1

[PATCH v2 15/19] MAINTAINERS: Add maintainer for Andes cache driver

[Mina Hui-Min Chou]

Add an entry for the Andes cache driver and its binding.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..afccbfecff79 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2054,6 +2054,13 @@ S:	Supported
 F:	Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
 F:	drivers/watchdog/atcwdt200_wdt.c
 
+ANDES CACHE DRIVER
+M:	Mina Hui-Min Chou <minachou@andestech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/cache/andestech,llcache.yaml
+F:	drivers/cache/andes_llcache.c
+F:	include/linux/soc/andes/csr.h
+
 ANDROID DRIVERS
 M:	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 M:	Arve Hjønnevåg <arve@android.com>
-- 
2.34.1

[PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs

[Mina Hui-Min Chou]

ERRATA_ANDES_CMO depends on ARCH_R9A07G043, so it can only be enabled
for the Renesas RZ/Five, although other Andes SoCs such as those built
on the A27L2 need it too. Drop the dependency, and select
ANDES_LLCACHE and CACHEMAINT_FOR_DMA so that the errata always comes
with its cache driver, which ARCH_R9A07G043 used to guarantee.

As ERRATA_ANDES_CMO is default y, it is now also enabled in the generic
riscv defconfig. The errata only acts on Andes cores at boot, so other
platforms are not affected.

RZ/Five still gets uncached memory for coherent DMA allocations from the
DMA_GLOBAL_POOL that ARCH_R9A07G043 selects. This patch only covers
cache maintenance for streaming DMA; how other platforms provide uncached
memory stays platform specific.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 arch/riscv/Kconfig.errata | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 4f77b3c6d7fd..3c43e065aa01 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -12,7 +12,9 @@ config ERRATA_ANDES
 
 config ERRATA_ANDES_CMO
 	bool "Apply Andes cache management errata"
-	depends on ERRATA_ANDES && ARCH_R9A07G043
+	depends on ERRATA_ANDES
+	select ANDES_LLCACHE
+	select CACHEMAINT_FOR_DMA
 	select RISCV_DMA_NONCOHERENT
 	default y
 	help
-- 
2.34.1

[PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores

[Mina Hui-Min Chou]

The Andes cache errata probe only runs on AX45MP: it matches
ANDES_AX45MP_MARCHID/MIMPID and then asks the Andes SBI extension
whether IOCP is missing. Other Andes cores that need CCTL-based cache
maintenance, such as the A27L2, which has neither IOCP nor Zicbom, are
silently skipped.

The IOCP_SW_WORKAROUND SBI call cannot simply be used on every Andes
core: OpenSBI checks the IOCP bit in mmsc_cfg[47], which only exists on
RV64 cores. RV32 cores such as the A45MP report IOCP in mmsc_cfg2
instead, and cores such as the A25/A27 do not support IOCP at all.

Keep the existing SBI-based check for AX45MP. On other Andes cores, use
the Andes CCTL operations for cache maintenance when the core does not
implement Zicbom.

As the probe is no longer only about IOCP, rename errata_probe_iocp()
to errata_probe_andes_cache(), ERRATA_ANDES_NO_IOCP to
ERRATA_ANDES_CACHE, and the ERRATA_ANDES prompt from "Andes AX45MP
errata" to "Andes errata".

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 arch/riscv/Kconfig.errata                    |  2 +-
 arch/riscv/errata/andes/errata.c             | 13 +++++++------
 arch/riscv/include/asm/errata_list_vendors.h |  2 +-
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 3c43e065aa01..ca8e52bee497 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -1,7 +1,7 @@
 menu "CPU errata selection"
 
 config ERRATA_ANDES
-	bool "Andes AX45MP errata"
+	bool "Andes errata"
 	depends on RISCV_SBI
 	help
 	  All Andes errata Kconfig depend on this Kconfig. Disabling
diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index dcc9d1ee5ffd..530d2df216e0 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -39,7 +39,7 @@ static long ax45mp_iocp_sw_workaround(void)
 	return ret.error ? 0 : ret.value;
 }
 
-static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
+static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)
 {
 	static bool done;
 
@@ -51,11 +51,12 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
 
 	done = true;
 
-	if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
-		return;
-
-	if (!ax45mp_iocp_sw_workaround())
+	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
+		if (!ax45mp_iocp_sw_workaround())
+			return;
+	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
 		return;
+	}
 
 	/* Set this just to make core cbo code happy */
 	riscv_cbom_block_size = 1;
@@ -69,7 +70,7 @@ void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct al
 	BUILD_BUG_ON(ERRATA_ANDES_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
 
 	if (stage == RISCV_ALTERNATIVES_BOOT)
-		errata_probe_iocp(stage, archid, impid);
+		errata_probe_andes_cache(stage, archid, impid);
 
 	/* we have nothing to patch here ATM so just return back */
 }
diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h
index 02b5ab0d23a8..d2fbef69f421 100644
--- a/arch/riscv/include/asm/errata_list_vendors.h
+++ b/arch/riscv/include/asm/errata_list_vendors.h
@@ -4,7 +4,7 @@
 #define ASM_ERRATA_LIST_VENDORS_H
 
 #ifdef CONFIG_ERRATA_ANDES
-#define	ERRATA_ANDES_NO_IOCP 0
+#define	ERRATA_ANDES_CACHE 0
 #define	ERRATA_ANDES_NUMBER 1
 #endif
 
-- 
2.34.1

[PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five

[Mina Hui-Min Chou]

The SBI-based IOCP check was added for Renesas RZ/Five (R9A07G043F),
the only upstream-supported SoC whose AX45MP has no IOCP. It matches
the AX45MP marchid and the mimpid of the RZ/Five core, but it is built
into every kernel with ERRATA_ANDES_CMO, so the SBI call is issued even
when the kernel does not support RZ/Five.

Move the match into soc_is_r9a07g043f() and make it also require
ARCH_R9A07G043. Kernels without RZ/Five support then skip the SBI call
and take the generic Andes cache errata path. No other upstream-
supported SoC uses this AX45MP mimpid, so their behavior does not
change.

While at it, rename ax45mp_iocp_sw_workaround() to
r9a07g043f_iocp_sw_workaround(), as the check is only used for RZ/Five.

Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
---
 arch/riscv/errata/andes/errata.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index 530d2df216e0..f2535a81b1e2 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -25,7 +25,7 @@
 
 #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
 
-static long ax45mp_iocp_sw_workaround(void)
+static long r9a07g043f_iocp_sw_workaround(void)
 {
 	struct sbiret ret;
 
@@ -39,6 +39,13 @@ static long ax45mp_iocp_sw_workaround(void)
 	return ret.error ? 0 : ret.value;
 }
 
+static bool soc_is_r9a07g043f(unsigned long arch_id, unsigned long impid)
+{
+	return IS_ENABLED(CONFIG_ARCH_R9A07G043) &&
+	       arch_id == ANDES_AX45MP_MARCHID &&
+	       impid == ANDES_AX45MP_MIMPID;
+}
+
 static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)
 {
 	static bool done;
@@ -51,8 +58,8 @@ static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id,
 
 	done = true;
 
-	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
-		if (!ax45mp_iocp_sw_workaround())
+	if (soc_is_r9a07g043f(arch_id, impid)) {
+		if (!r9a07g043f_iocp_sw_workaround())
 			return;
 	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
 		return;
-- 
2.34.1

Re: [PATCH v2 18/19] riscv: errata: andes: limit the IOCP workaround to RZ/Five

[Conor Dooley]

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On Fri, Nov 13, 2026 at 03:11:42PM +0800, Mina Hui-Min Chou wrote:
> The SBI-based IOCP check was added for Renesas RZ/Five (R9A07G043F),
> the only upstream-supported SoC whose AX45MP has no IOCP. It matches
> the AX45MP marchid and the mimpid of the RZ/Five core, but it is built
> into every kernel with ERRATA_ANDES_CMO, so the SBI call is issued even
> when the kernel does not support RZ/Five.
> 
> Move the match into soc_is_r9a07g043f() and make it also require
> ARCH_R9A07G043. Kernels without RZ/Five support then skip the SBI call
> and take the generic Andes cache errata path. No other upstream-
> supported SoC uses this AX45MP mimpid, so their behavior does not
> change.

But a device using this soc that doesn't have a dts in mainline won't
function properly, so this is fragile. Why not just do it properly and
check for RZ/Five specifically?
Can check for of_machine_is_compatible() probably?

> 
> While at it, rename ax45mp_iocp_sw_workaround() to
> r9a07g043f_iocp_sw_workaround(), as the check is only used for RZ/Five.
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  arch/riscv/errata/andes/errata.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index 530d2df216e0..f2535a81b1e2 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -25,7 +25,7 @@
>  
>  #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
>  
> -static long ax45mp_iocp_sw_workaround(void)
> +static long r9a07g043f_iocp_sw_workaround(void)
>  {
>  	struct sbiret ret;
>  
> @@ -39,6 +39,13 @@ static long ax45mp_iocp_sw_workaround(void)
>  	return ret.error ? 0 : ret.value;
>  }
>  
> +static bool soc_is_r9a07g043f(unsigned long arch_id, unsigned long impid)
> +{
> +	return IS_ENABLED(CONFIG_ARCH_R9A07G043) &&
> +	       arch_id == ANDES_AX45MP_MARCHID &&
> +	       impid == ANDES_AX45MP_MIMPID;
> +}
> +
>  static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)
>  {
>  	static bool done;
> @@ -51,8 +58,8 @@ static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id,
>  
>  	done = true;
>  
> -	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
> -		if (!ax45mp_iocp_sw_workaround())
> +	if (soc_is_r9a07g043f(arch_id, impid)) {
> +		if (!r9a07g043f_iocp_sw_workaround())
>  			return;
>  	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
>  		return;
> -- 
> 2.34.1
> 

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Re: [PATCH v2 17/19] riscv: errata: andes: generalize cache errata for Andes cores

[Conor Dooley]

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On Fri, Nov 13, 2026 at 03:11:41PM +0800, Mina Hui-Min Chou wrote:
> The Andes cache errata probe only runs on AX45MP: it matches
> ANDES_AX45MP_MARCHID/MIMPID and then asks the Andes SBI extension
> whether IOCP is missing. Other Andes cores that need CCTL-based cache
> maintenance, such as the A27L2, which has neither IOCP nor Zicbom, are
> silently skipped.
> 
> The IOCP_SW_WORKAROUND SBI call cannot simply be used on every Andes
> core: OpenSBI checks the IOCP bit in mmsc_cfg[47], which only exists on
> RV64 cores. RV32 cores such as the A45MP report IOCP in mmsc_cfg2
> instead, and cores such as the A25/A27 do not support IOCP at all.
> 
> Keep the existing SBI-based check for AX45MP. On other Andes cores, use
> the Andes CCTL operations for cache maintenance when the core does not
> implement Zicbom.
> 
> As the probe is no longer only about IOCP, rename errata_probe_iocp()
> to errata_probe_andes_cache(), ERRATA_ANDES_NO_IOCP to
> ERRATA_ANDES_CACHE, and the ERRATA_ANDES prompt from "Andes AX45MP
> errata" to "Andes errata".
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  arch/riscv/Kconfig.errata                    |  2 +-
>  arch/riscv/errata/andes/errata.c             | 13 +++++++------
>  arch/riscv/include/asm/errata_list_vendors.h |  2 +-
>  3 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 3c43e065aa01..ca8e52bee497 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -1,7 +1,7 @@
>  menu "CPU errata selection"
>  
>  config ERRATA_ANDES
> -	bool "Andes AX45MP errata"
> +	bool "Andes errata"
>  	depends on RISCV_SBI
>  	help
>  	  All Andes errata Kconfig depend on this Kconfig. Disabling
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index dcc9d1ee5ffd..530d2df216e0 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -39,7 +39,7 @@ static long ax45mp_iocp_sw_workaround(void)
>  	return ret.error ? 0 : ret.value;
>  }
>  
> -static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
> +static void errata_probe_andes_cache(unsigned int stage, unsigned long arch_id, unsigned long impid)

Just call it probe so that you dont rename it again when the next
erratum shows up?

>  {
>  	static bool done;
>  
> @@ -51,11 +51,12 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
>  
>  	done = true;
>  
> -	if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
> -		return;
> -
> -	if (!ax45mp_iocp_sw_workaround())
> +	if (arch_id == ANDES_AX45MP_MARCHID && impid == ANDES_AX45MP_MIMPID) {
> +		if (!ax45mp_iocp_sw_workaround())
> +			return;
> +	} else if (riscv_isa_extension_available(NULL, ZICBOM)) {
>  		return;
> +	}

Is this correct? The code goes on to always mark noncoherent stuff
supported, so this means that every andes device must then support
noncoherent. The commit message's wording isn't that strong.

>  
>  	/* Set this just to make core cbo code happy */

This comment is no longer accurate because you gave this value special
meaning elsewhere in the series.
That patch needs to change this comment.

Cheers,
Conor.

>  	riscv_cbom_block_size = 1;
> @@ -69,7 +70,7 @@ void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct al
>  	BUILD_BUG_ON(ERRATA_ANDES_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
>  
>  	if (stage == RISCV_ALTERNATIVES_BOOT)
> -		errata_probe_iocp(stage, archid, impid);
> +		errata_probe_andes_cache(stage, archid, impid);
>  
>  	/* we have nothing to patch here ATM so just return back */
>  }
> diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h
> index 02b5ab0d23a8..d2fbef69f421 100644
> --- a/arch/riscv/include/asm/errata_list_vendors.h
> +++ b/arch/riscv/include/asm/errata_list_vendors.h
> @@ -4,7 +4,7 @@
>  #define ASM_ERRATA_LIST_VENDORS_H
>  
>  #ifdef CONFIG_ERRATA_ANDES
> -#define	ERRATA_ANDES_NO_IOCP 0
> +#define	ERRATA_ANDES_CACHE 0
>  #define	ERRATA_ANDES_NUMBER 1
>  #endif
>  
> -- 
> 2.34.1
> 

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Re: [PATCH v2 16/19] riscv: errata: andes: allow ERRATA_ANDES_CMO on all Andes SoCs

[Conor Dooley]

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On Fri, Nov 13, 2026 at 03:11:40PM +0800, Mina Hui-Min Chou wrote:
> ERRATA_ANDES_CMO depends on ARCH_R9A07G043, so it can only be enabled
> for the Renesas RZ/Five, although other Andes SoCs such as those built
> on the A27L2 need it too. Drop the dependency, and select
> ANDES_LLCACHE and CACHEMAINT_FOR_DMA so that the errata always comes
> with its cache driver, which ARCH_R9A07G043 used to guarantee.
> 
> As ERRATA_ANDES_CMO is default y, it is now also enabled in the generic
> riscv defconfig. The errata only acts on Andes cores at boot, so other
> platforms are not affected.
> 
> RZ/Five still gets uncached memory for coherent DMA allocations from the
> DMA_GLOBAL_POOL that ARCH_R9A07G043 selects. This patch only covers
> cache maintenance for streaming DMA; how other platforms provide uncached
> memory stays platform specific.
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  arch/riscv/Kconfig.errata | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index 4f77b3c6d7fd..3c43e065aa01 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -12,7 +12,9 @@ config ERRATA_ANDES
>  
>  config ERRATA_ANDES_CMO
>  	bool "Apply Andes cache management errata"
> -	depends on ERRATA_ANDES && ARCH_R9A07G043
> +	depends on ERRATA_ANDES
> +	select ANDES_LLCACHE
> +	select CACHEMAINT_FOR_DMA

If you're selecting it here, can you not drop it from the renesas soc
Kconfig file?

>  	select RISCV_DMA_NONCOHERENT
>  	default y
>  	help
> -- 
> 2.34.1
> 

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Re: [PATCH v2 13/19] dt-bindings: cache: rename andestech,ax45mp-cache to andestech,llcache

[Conor Dooley]

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On Fri, Nov 13, 2026 at 03:11:37PM +0800, Mina Hui-Min Chou wrote:
> The binding now covers Andes last level caches beyond AX45MP and uses
> andestech,llcache as the generic compatible. Rename the file to match
> it.
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>

Squash this with the other binding patch please.

> ---
>  .../{andestech,ax45mp-cache.yaml => andestech,llcache.yaml}     | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>  rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,llcache.yaml} (97%)
> 
> diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,llcache.yaml
> similarity index 97%
> rename from Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> rename to Documentation/devicetree/bindings/cache/andestech,llcache.yaml
> index da9688cc95f7..f97038d39b0e 100644
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,llcache.yaml
> @@ -2,7 +2,7 @@
>  # Copyright (C) 2023 Renesas Electronics Corp.
>  %YAML 1.2
>  ---
> -$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
> +$id: http://devicetree.org/schemas/cache/andestech,llcache.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
>  title: Andestech Last Level Cache Controller
> -- 
> 2.34.1
> 

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Re: [PATCH v2 12/19] dt-bindings: cache: andestech: update schema for generic LLC support

[Conor Dooley]

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On Fri, Nov 13, 2026 at 03:11:36PM +0800, Mina Hui-Min Chou wrote:
> The last level cache controller of Andes cores is not specific to
> AX45MP. Other Andes cores, such as the A27L2, use the same controller
> with the same register interface, but the binding only accepts
> andestech,ax45mp-cache. Add andestech,llcache for them, and describe
> the binding as an Andes last level cache rather than an AX45MP L2
> cache.
> 
> The cache-level, cache-sets and cache-size constraints describe the
> AX45MP L2 cache, so apply them to andestech,ax45mp-cache only. The LLC
> of other Andes cores can be level 3 and have other geometries, so
> allow cache-level 3 and require cache-sets only for AX45MP. Match
> renesas,r9a07g043f-ax45mp-cache explicitly instead of through the else
> branch, which would otherwise also apply to andestech,llcache.
> 
> Also add an example for andestech,llcache, and add myself as a
> maintainer of the binding.
> 
> Signed-off-by: Mina Hui-Min Chou <minachou@andestech.com>
> ---
>  .../cache/andestech,ax45mp-cache.yaml         | 71 ++++++++++++++-----
>  1 file changed, 54 insertions(+), 17 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> index b135ffa4ab6b..da9688cc95f7 100644
> --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> @@ -5,14 +5,15 @@
>  $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: Andestech AX45MP L2 Cache Controller
> +title: Andestech Last Level Cache Controller
>  
>  maintainers:
>    - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +  - Mina Hui-Min Chou <minachou@andestech.com>
>  
>  description:
> -  A level-2 cache (L2C) is used to improve the system performance by providing
> -  a large amount of cache line entries and reasonable access delays. The L2C
> +  A last level cache (LLC) is used to improve the system performance by providing
> +  a large amount of cache line entries and reasonable access delays. The LLC
>    is shared between cores, and a non-inclusive non-exclusive policy is used.
>  
>  select:
> @@ -21,18 +22,23 @@ select:
>        contains:
>          enum:
>            - andestech,ax45mp-cache
> +          - andestech,llcache
>  
>    required:
>      - compatible
>  
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - andestech,qilai-ax45mp-cache
> -          - renesas,r9a07g043f-ax45mp-cache
> -      - const: andestech,ax45mp-cache
> -      - const: cache
> +    oneOf:
> +      - items:
> +          - enum:
> +              - andestech,qilai-ax45mp-cache
> +              - renesas,r9a07g043f-ax45mp-cache
> +          - const: andestech,ax45mp-cache
> +          - const: cache
> +      - items:
> +          - const: andestech,llcache
> +          - const: cache

Device specific compatibles are mandatory. I would accept this patch
with a
          - not: {}
            description: Need a SoC specific compatible
like the safexcel eip binding.

pw-bot: changes-requested

Thanks,
Conor.


>  
>    reg:
>      maxItems: 1
> @@ -44,13 +50,11 @@ properties:
>      const: 64
>  
>    cache-level:
> -    const: 2
> +    enum: [2, 3]
>  
> -  cache-sets:
> -    enum: [1024, 2048]
> +  cache-sets: true
>  
> -  cache-size:
> -    enum: [131072, 262144, 524288, 1048576, 2097152]
> +  cache-size: true
>  
>    cache-unified: true
>  
> @@ -64,7 +68,6 @@ required:
>    - interrupts
>    - cache-line-size
>    - cache-level
> -  - cache-sets
>    - cache-size
>    - cache-unified
>  
> @@ -73,15 +76,36 @@ allOf:
>        properties:
>          compatible:
>            contains:
> -            const: andestech,qilai-ax45mp-cache
> +            const: andestech,ax45mp-cache
> +    then:
> +      properties:
> +        cache-level:
> +          const: 2
> +        cache-sets:
> +          enum: [1024, 2048]
> +        cache-size:
> +          enum: [131072, 262144, 524288, 1048576, 2097152]
> +      required:
> +        - cache-sets
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: andestech,qilai-ax45mp-cache
>      then:
>        properties:
>          cache-sets:
>            const: 2048
>          cache-size:
>            const: 2097152
> -    else:
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a07g043f-ax45mp-cache
> +    then:
>        properties:
>          cache-sets:
>            const: 1024
> @@ -101,3 +125,16 @@ examples:
>          cache-size = <262144>;
>          cache-unified;
>      };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    cache-controller@e0500000 {
> +        compatible = "andestech,llcache", "cache";
> +        reg = <0xe0500000 0x10000>;
> +        interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> +        cache-line-size = <64>;
> +        cache-level = <2>;
> +        cache-size = <262144>;
> +        cache-unified;
> +    };
> -- 
> 2.34.1
> 

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