Re: [PATCH v3 15/21] sched/cache: Disable cache aware scheduling for processes with high thread counts

[Madadi Vineeth Reddy <vineethr@linux.ibm.com>]

On 11/02/26 03:48, Tim Chen wrote:
> From: Chen Yu <yu.c.chen@intel.com>
> 
> A performance regression was observed by Prateek when running hackbench
> with many threads per process (high fd count). To avoid this, processes
> with a large number of active threads are excluded from cache-aware
> scheduling.
> 
> With sched_cache enabled, record the number of active threads in each
> process during the periodic task_cache_work(). While iterating over
> CPUs, if the currently running task belongs to the same process as the
> task that launched task_cache_work(), increment the active thread count.
> 
> If the number of active threads within the process exceeds the number
> of Cores(divided by SMTs number) in the LLC, do not enable cache-aware
> scheduling. For users who wish to perform task aggregation regardless,
> a debugfs knob is provided for tuning in a subsequent patch.
> 
> Suggested-by: K Prateek Nayak <kprateek.nayak@amd.com>
> Suggested-by: Aaron Lu <ziqianlu@bytedance.com>
> Co-developed-by: Tim Chen <tim.c.chen@linux.intel.com>
> Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
> Signed-off-by: Chen Yu <yu.c.chen@intel.com>
> ---
> 
> Notes:
>     v2->v3:
>     Put the calculating of nr_running_avg and the use of it into 1 patch.
>     (Peter Zijlstra)
>     
>     Use guard(rcu)() when calculating the number of active threads of the
>     process.
>     (Peter Zijlstra)
>     
>     Introduce update_avg_scale() rather than using update_avg() to fit
>     system with small LLC.
>     (Aaron Lu)
> 
>  include/linux/sched.h |  1 +
>  kernel/sched/fair.c   | 59 ++++++++++++++++++++++++++++++++++++++++---
>  2 files changed, 57 insertions(+), 3 deletions(-)
> 
> diff --git a/include/linux/sched.h b/include/linux/sched.h
> index c98bd1c46088..511c9b263386 100644
> --- a/include/linux/sched.h
> +++ b/include/linux/sched.h
> @@ -2346,6 +2346,7 @@ struct sched_cache_stat {
>  	struct sched_cache_time __percpu *pcpu_sched;
>  	raw_spinlock_t lock;
>  	unsigned long epoch;
> +	u64 nr_running_avg;
>  	int cpu;
>  } ____cacheline_aligned_in_smp;
>  
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index d1145997b88d..86b6b08e7e1e 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -1223,6 +1223,19 @@ static inline bool valid_llc_buf(struct sched_domain *sd,
>  	return valid_llc_id(id);
>  }
>  
> +static bool exceed_llc_nr(struct mm_struct *mm, int cpu)
> +{
> +	int smt_nr = 1;
> +
> +#ifdef CONFIG_SCHED_SMT
> +	if (sched_smt_active())
> +		smt_nr = cpumask_weight(cpu_smt_mask(cpu));
> +#endif
> +
> +	return !fits_capacity((mm->sc_stat.nr_running_avg * smt_nr),
> +			per_cpu(sd_llc_size, cpu));


On Power10/Power11 with SMT4 and LLC size of 4, this check
effectively disables cache-aware scheduling for any process.

I raised this point in v1 as well. Increasing the threshold
doesn't seem like a viable solution either, as that would regress
hackbench/ebizzy.

Is there a way to make this useful for architectures with small LLC
sizes? One possible approach we were exploring is to have LLC at a
hemisphere level that comprise multiple SMT4 cores.

Thanks,
Vineeth

> +}
> +
>  static void account_llc_enqueue(struct rq *rq, struct task_struct *p)
>  {
>  	struct sched_domain *sd;
> @@ -1417,7 +1430,8 @@ void account_mm_sched(struct rq *rq, struct task_struct *p, s64 delta_exec)
>  	 */
>  	if (time_after(epoch,
>  		       READ_ONCE(mm->sc_stat.epoch) + EPOCH_LLC_AFFINITY_TIMEOUT) ||
> -	    get_nr_threads(p) <= 1) {
> +	    get_nr_threads(p) <= 1 ||
> +	    exceed_llc_nr(mm, cpu_of(rq))) {
>  		if (mm->sc_stat.cpu != -1)
>  			mm->sc_stat.cpu = -1;
>  	}
> @@ -1458,13 +1472,31 @@ static void task_tick_cache(struct rq *rq, struct task_struct *p)
>  	}
>  }
>  
> +static inline void update_avg_scale(u64 *avg, u64 sample)
> +{
> +	int factor = per_cpu(sd_llc_size, raw_smp_processor_id());
> +	s64 diff = sample - *avg;
> +	u32 divisor;
> +
> +	/*
> +	 * Scale the divisor based on the number of CPUs contained
> +	 * in the LLC. This scaling ensures smaller LLC domains use
> +	 * a smaller divisor to achieve more precise sensitivity to
> +	 * changes in nr_running, while larger LLC domains are capped
> +	 * at a maximum divisor of 8 which is the default smoothing
> +	 * factor of EWMA in update_avg().
> +	 */
> +	divisor = clamp_t(u32, (factor >> 2), 2, 8);
> +	*avg += div64_s64(diff, divisor);
> +}
> +
>  static void task_cache_work(struct callback_head *work)
>  {
> -	struct task_struct *p = current;
> +	struct task_struct *p = current, *cur;
>  	struct mm_struct *mm = p->mm;
>  	unsigned long m_a_occ = 0;
>  	unsigned long curr_m_a_occ = 0;
> -	int cpu, m_a_cpu = -1;
> +	int cpu, m_a_cpu = -1, nr_running = 0;
>  	cpumask_var_t cpus;
>  
>  	WARN_ON_ONCE(work != &p->cache_work);
> @@ -1474,6 +1506,13 @@ static void task_cache_work(struct callback_head *work)
>  	if (p->flags & PF_EXITING)
>  		return;
>  
> +	if (get_nr_threads(p) <= 1) {
> +		if (mm->sc_stat.cpu != -1)
> +			mm->sc_stat.cpu = -1;
> +
> +		return;
> +	}
> +
>  	if (!zalloc_cpumask_var(&cpus, GFP_KERNEL))
>  		return;
>  
> @@ -1497,6 +1536,12 @@ static void task_cache_work(struct callback_head *work)
>  					m_occ = occ;
>  					m_cpu = i;
>  				}
> +				scoped_guard (rcu) {
> +					cur = rcu_dereference(cpu_rq(i)->curr);
> +					if (cur && !(cur->flags & (PF_EXITING | PF_KTHREAD)) &&
> +					    cur->mm == mm)
> +						nr_running++;
> +				}
>  			}
>  
>  			/*
> @@ -1540,6 +1585,7 @@ static void task_cache_work(struct callback_head *work)
>  		mm->sc_stat.cpu = m_a_cpu;
>  	}
>  
> +	update_avg_scale(&mm->sc_stat.nr_running_avg, nr_running);
>  	free_cpumask_var(cpus);
>  }
>  
> @@ -9988,6 +10034,13 @@ static enum llc_mig can_migrate_llc_task(int src_cpu, int dst_cpu,
>  	if (cpu < 0 || cpus_share_cache(src_cpu, dst_cpu))
>  		return mig_unrestricted;
>  
> +	/* skip cache aware load balance for single/too many threads */
> +	if (get_nr_threads(p) <= 1 || exceed_llc_nr(mm, dst_cpu)) {
> +		if (mm->sc_stat.cpu != -1)
> +			mm->sc_stat.cpu = -1;
> +		return mig_unrestricted;
> +	}
> +
>  	if (cpus_share_cache(dst_cpu, cpu))
>  		to_pref = true;
>  	else if (cpus_share_cache(src_cpu, cpu))